Redundancy Circuit Block Repair for Memory Defects
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Solution Overview
Problem
Current semiconductor memory devices face inefficiencies in correcting larger localized defects due to the high number of physical bits required for block repair, which can lead to unrepairable dice when a block repair is not available, and existing error correction codes (ECC) are ineffective for larger defect signatures.
Innovation Solution
The semiconductor memory device incorporates a redundancy circuit with a block repair mechanism that redirects data from defective blocks to redundant blocks within the ECC Parity/redundancy array, utilizing non-volatile elements like fuses to enable block repair by selectively enabling the block repair function when the number of defective cells exceeds the ECC's error correction capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block repair is used to correct larger localized defects, then the ability to correct larger defects is improved, but the space required in the non-volatile memory array increases significantly
Solution Approach 1:
The patent makes the ECC redundant bits serve dual purposes: continuing to correct scattered bit errors while also functioning as a block repair mechanism for localized defects. This multi-functionality eliminates the need for separate block repair storage, resolving the space consumption problem while maintaining defect correction capability.
Solution Approach 2:
The patent merges the ECC redundant bits with the block repair functionality, combining two previously separate error correction mechanisms into a unified system. The same redundant bits used for traditional ECC now also serve as the block repair data storage, consolidating resources and reducing overall space requirements.
2Reliability
If traditional ECC is used to correct errors, then scattered bit errors are corrected effectively, but larger localized defects cannot be corrected
Solution Approach 1:
The patent extends the ECC redundant bits to handle multiple defect types universally. Instead of being limited to scattered bit errors, the system now uses the same ECC mechanism to address both scattered errors and larger localized defects, achieving universal error correction across different defect patterns.
Solution Approach 2:
The patent introduces dynamic selection between ECC mode and block repair mode based on the type and extent of defects detected. The system adapts its correction strategy by selecting appropriate redundant bit allocation and correction algorithms according to whether the defect pattern matches scattered bit errors or larger localized defects.
3Reliability
If redundant rows and columns are used for repair, then defects are corrected during standard operation, but the number of physical bits required increases
Solution Approach 1:
The patent recovers and reuses the ECC redundant bits that would otherwise be dedicated solely to scattered error correction. By discarding the traditional separation between ECC and block repair functions, the system recovers the full utility of the redundant bits, allowing them to serve dual purposes and reducing the total quantity of physical bits needed for repair operations.
Solution Approach 2:
The patent changes the operational parameters of the redundant bits by allowing their function to switch between ECC correction and block repair based on defect characteristics. This parameter change enables the same physical bits to adapt their correction capacity, effectively reducing the total bit requirement compared to having fixed, dedicated repair structures.
Data Source
AI summary
Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair.