Voltage Regulator Dead Band Control for Stability and Power
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Solution Overview
Problem
Voltage regulator circuits, particularly low-dropout (LDO) regulators, face challenges in efficiency and stability across varying load conditions, especially when current draw changes significantly, as seen in microprocessor modes, due to issues with feedback loop gain and phase characteristics dependent on output load impedance.
Innovation Solution
The implementation of a voltage regulator circuit that utilizes a dead band region where the feedback loop does not actively adjust the output, employing a field-effect transistor (FET) as a pass transistor with a gate-control node that 'floats' when within the dead band, reducing power consumption and maintaining stability through binary control by comparators and pull-up/down circuits, independent of output FET characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a feedback loop is used to adjust operating parameters in response to load changes, then voltage regulation stability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using two comparators that alternately activate based on voltage thresholds. When Vout exceeds Vhigh, the first comparator triggers a discharge phase; when Vout drops below Vlow, the second comparator triggers a charge phase. This periodic switching creates a dead band region where the feedback loop is inactive, reducing power consumption while maintaining voltage regulation through controlled oscillation between thresholds.
2Reliability
If the feedback loop actively adjusts the output across all load conditions, then voltage stability is improved, but current consumption increases
Solution Approach 1:
The patent segments the voltage regulation range into three distinct regions: an upper region (Vout > Vhigh) where the first comparator activates, a dead band region (Vlow ≤ Vout ≤ Vhigh) where neither comparator is active, and a lower region (Vout < Vlow) where the second comparator activates. This segmentation allows the feedback loop to remain inactive during the dead band region, significantly reducing current consumption while maintaining adequate voltage stability through the bounded oscillation between thresholds.
3Speed
If pull-up/down circuits are continuously applied to the gate-control node, then voltage regulation response is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by using two comparators that alternately activate based on voltage thresholds. When Vout exceeds Vhigh, the first comparator triggers a discharge phase; when Vout drops below Vlow, the second comparator triggers a charge phase. This periodic switching creates a dead band region where the feedback loop is inactive, reducing power consumption while maintaining voltage regulation through controlled oscillation between thresholds.
Solution Approach 2:
The patent applies dynamics by making the pull-up/down circuit activation conditional rather than continuous. The first pull-down circuit is enabled only when Vout > Vhigh, and the second pull-up circuit is enabled only when Vout < Vlow. This dynamic, condition-based activation allows the system to maintain fast response when regulation is needed while consuming minimal power when the output voltage remains within acceptable bounds.
Data Source
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AI summary
A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.