Memory Macro Bypass Paths for SRAM ECC Testing
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in efficiently executing tests for both the SRAM core and ECC circuits within a memory macro, requiring complex circuit structures and additional test patterns, which can increase circuit size and performance impact.
Innovation Solution
A semiconductor integrated circuit design that includes a memory macro with a first ECC circuit for error detection and correction, a SRAM core for data storage, an ECC storage portion, and bypass paths for scan and memory tests, utilizing existing latch circuits and selectors to separate data and code paths, allowing for independent testing of SRAM and ECC circuits without significant circuit expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC circuits are provided outside the memory macro for error detection and correction, then error correction capability is improved, but device complexity increases and test execution becomes less efficient
Solution Approach 1:
The patent merges the ECC circuits with the memory macro by integrating them within the same macro structure. The ECC storage portion is coupled to the memory core, and the ECC circuits are positioned to receive data directly from the memory core, creating a unified memory macro that combines both storage and error correction functionality. This reduces overall device complexity while maintaining error correction capability.
Solution Approach 2:
The memory macro is designed to serve multiple functions: data storage in the memory core, error detection and correction through the ECC circuits, and versatile testing capabilities. The same integrated structure supports both normal operation modes (read/write with ECC) and test modes (scan tests, memory tests), eliminating the need for separate external ECC circuits and enabling efficient combined testing.
2Reliability
If separate test patterns are used for testing both SRAM core and ECC circuits, then testing completeness is improved, but productivity decreases due to increased test complexity and time
Solution Approach 1:
The patent combines the testing of the SRAM core and ECC circuits into a single integrated test process. The memory macro's unified structure allows test patterns to be applied once and automatically propagate through both the memory core and ECC circuits. The bypass paths enable test data to flow through either the memory core or the ECC storage portion, allowing comprehensive testing of both components and their interactions without requiring separate test sequences.
Solution Approach 2:
The integrated memory macro structure provides universal testing capability that handles both SRAM core testing and ECC circuit testing through the same test infrastructure. The bypass paths and coupled architecture allow a single test pattern application to verify multiple functions (memory storage, ECC generation, ECC verification), significantly improving test execution efficiency while maintaining complete testing coverage.
3Measurement precision
If additional test patterns are introduced to test both memory and ECC circuits, then measurement precision is improved, but loss of time increases due to extended test sequences
Solution Approach 1:
The patent merges the test measurement processes for the memory core and ECC circuits into a single streamlined operation. The integrated architecture allows test patterns to be applied once and automatically measured across both components simultaneously. The bypass paths enable efficient data flow during testing, allowing complete measurement of memory functionality and ECC performance without requiring sequential separate test sequences, thus reducing time loss while maintaining measurement precision.
Data Source
AI summary
In general, according to one embodiment, there is provided a semiconductor integrated circuit including a memory macro. The memory macro includes a first ECC circuit that generates a code corresponding to input data, a memory core including a data storage portion on which reading and writing of data is performed, and an ECC storage portion on which reading and writing of a code is performed, a second ECC circuit that executes, based on data and code read from the memory core, error detection or correction of the data, and circuits that form a path in which data flows to bypass the memory core in a scan test, and form a path in which data flows through each of the data storage portion and the ECC storage portion in a memory test.