Semiconductor Test Device Pattern Memory Segmentation
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Solution Overview
Problem
The increasing data capacity required for pattern memory in semiconductor testing devices to achieve high fault coverage leads to increased costs and testing times, particularly for applications requiring high reliability like automobiles and industrial uses, due to the need for high-speed SRAM and additional circuitry, which also results in higher power consumption and heat generation.
Innovation Solution
A semiconductor-product testing device that rewrites its pattern memory with new test pattern portions during testing, allowing for reduced data capacity in both pattern and fail memories, and utilizes wireless data transfer to efficiently manage and divide test patterns across multiple channels, thereby reducing the need for extensive SRAM and circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-speed SRAM is used to increase pattern memory capacity for high fault coverage, then testing speed and fault coverage are improved, but device cost and power consumption increase
Solution Approach 1:
The test pattern data is divided into multiple segments that are stored in a smaller-capacity memory. The segmentation allows the system to process and test semiconductor products using divided pattern portions, achieving high fault coverage without requiring a single large-capacity high-speed SRAM, thus reducing device cost and power consumption while maintaining testing speed.
2Reliability
If pattern memory capacity is increased to handle larger data amounts for high reliability applications, then fault coverage is improved, but testing time and device cost increase
Solution Approach 1:
Pattern data is pre-divided into multiple portions and stored in advance in a smaller-capacity memory. This preliminary segmentation and storage strategy enables the system to quickly access and process test patterns during semiconductor testing, achieving high fault coverage for reliable applications without increasing testing time or requiring large-capacity memory.
3Productivity
If transfer rate of pattern data is increased to reduce testing time, then productivity is improved, but power consumption and heat generation increase
Solution Approach 1:
Pattern data is segmented into multiple smaller portions that can be efficiently transferred and processed. This segmentation enables optimized data transfer rates that reduce the power consumption and heat generation associated with high-speed data transfer, while maintaining high productivity through efficient processing of divided pattern portions during semiconductor testing.
Data Source
AI summary
A semiconductor-product testing device that supplies a test pattern for testing a semiconductor product to the semiconductor product includes a pattern memory that stores a part of the test pattern. The pattern memory is rewritten during a time when the semiconductor product is tested by a part of the test pattern stored in the pattern memory included in the semiconductor-product testing device.