Flash Memory Error Detection Protocol for Signal Integrity
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Solution Overview
Problem
As memory density increases and throughput demands higher operating frequencies, there is a growing potential for errors in the transmission of control and data signals between memory controllers and devices due to propagation delays and noise, leading to incorrect transfer of access control signals.
Innovation Solution
Implementing an error detection protocol in memory systems that includes generating and verifying error detection signals corresponding to command and address information, using a combination of command error detection bits and address error detection bits, which are time-multiplexed with the access control signals, to ensure accurate signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating frequency is increased to meet throughput demands, then productivity is improved, but reliability deteriorates due to propagation delays and noise effects distorting control signals
Solution Approach 1:
The patent implements error detection through feedback mechanisms where the memory device sends acknowledgment signals back to the controller. The controller transmits control signals and receives feedback about their successful reception and execution, allowing for error detection and correction in the high-speed communication channel.
Solution Approach 2:
The patent employs preliminary actions by having the memory device prepare acknowledgment signals in advance and by implementing error detection codes that are transmitted alongside control signals. This preliminary preparation allows the system to maintain reliability even at higher operating frequencies where propagation delays occur.
2Reliability
If error detection protocol is implemented, then reliability is improved, but device complexity increases due to additional control signals and verification logic
Solution Approach 1:
The patent merges error detection functionality with the existing control signal transmission structure. The error detection codes are combined with command and address signals, and the acknowledgment mechanism is integrated into the existing data bus communication, rather than adding separate dedicated error detection channels.
Solution Approach 2:
The acknowledgment signals serve multiple functions: they confirm receipt of control signals, indicate successful operation execution, and provide error detection capabilities. This multi-functionality reduces the need for separate dedicated error detection mechanisms, thereby limiting the increase in device complexity.
Data Source
AI summary
In accordance with the disclosure, there is provided a memory device configured to implement an error detection protocol. The memory device includes a memory array and a first input for receiving a control signal corresponding to a command cycle. The memory device also includes a second input for receiving an access control signal during a command cycle and for receiving an error detection signal during the command cycle, wherein the error detection signal includes information corresponding to the access control signal. The memory device further includes control logic configured to verify the correctness of the access control signal by a comparison with the error detection signal and perform an operation on the memory array during the command cycle when the correctness of the access control signal is verified.