Memory Row Remapping to Mitigate Bit Errors
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Solution Overview
Problem
Memory devices face challenges in managing bit errors, particularly when the quantity of redundant rows is limited, leading to a higher likelihood of accessing rows with bit errors.
Innovation Solution
The memory device remaps the row index associated with a row having a bit error to a different row in standard memory, or transmits an indication to the host device about rows with bit errors, allowing the host to avoid accessing them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device uses redundant rows to replace rows with bit errors, then the reliability of data storage is improved, but the device complexity increases and the quantity of available storage space decreases
Solution Approach 1:
The memory device performs self-diagnosis through test operations to identify rows with bit errors, and automatically remaps these defective rows to redundant rows without external intervention. This self-service mechanism maintains reliability while avoiding the need for complex external error management systems.
Solution Approach 2:
The memory device performs test operations during initialization or idle periods to proactively identify rows with bit errors before they affect normal operation. By performing this preliminary detection and remapping action in advance, the system ensures reliability without adding complexity to the critical data path operations.
2Reliability
If the memory device remaps row indices to redundant rows, then the likelihood of accessing error-free data is improved, but the productivity of memory operations decreases due to additional remapping overhead
Solution Approach 1:
The memory device performs remapping operations during idle periods or initialization phases rather than during active data operations. By completing the remapping of defective rows to redundant rows in advance, the system ensures that normal read/write operations can proceed without remapping overhead, thus maintaining productivity while ensuring access to error-free data.
Solution Approach 2:
The memory controller automatically manages the remapping process without requiring host intervention or additional processing during normal operations. The remapping information is stored in a mapping structure that the controller consults automatically, eliminating the need for host device to perform error checking or remapping operations that would reduce productivity.
3Reliability
If the host device is informed about rows with bit errors, then the host can avoid accessing defective rows and improve data reliability, but the loss of information increases due to restricted access to memory addresses
Solution Approach 1:
The memory device introduces a mapping mechanism that acts as an intermediary between the host device and the physical memory addresses. When the host requests access to a logical address, the mapping mechanism translates it to the corresponding physical address, automatically redirecting requests from defective rows to redundant rows. This intermediary layer maintains full host access to the logical address space while ensuring that only functional memory locations are accessed, thus preventing information loss while improving reliability.
Solution Approach 2:
The memory device creates a virtual copy of the address space through remapping, where defective physical addresses are copied to redundant physical addresses. This allows the host to access the full logical address space without knowing about the physical defects, as the mapping layer transparently redirects to working memory locations, thereby maintaining both reliability and full information accessibility.
Data Source
AI summary
Methods, systems, and devices for bit retiring to mitigate bit errors are described. A memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. The memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. Additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. The memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.