Memory Circuit Redundant Decoder Control for Repair Efficiency
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Solution Overview
Problem
Existing memory circuit devices require excessive data operations and transmissions to identify and replace failed storage lines, which lowers repair efficiency due to the need for external controller involvement in storing and analyzing failed line information.
Innovation Solution
A memory circuit device with a redundant decoder control circuit that activates redundant storage lines based on addresses received from a testing device, eliminating the need for external controller intervention by directly replacing failed storage lines with redundant ones within the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If information regarding the failed storage line is stored in a storage unit before analysis by the external controller, then the failed storage line can be identified and replaced, but data operations and transmissions increase, thereby lowering repair efficiency
Solution Approach 1:
The patent extracts the repair control function from the external controller and relocates it to the memory circuit device itself. The redundant decoder control circuit is integrated within the memory device to directly receive the address of the failed storage line from the testing device and activate the corresponding redundant storage line, eliminating the need for external storage and analysis of failure information.
Solution Approach 2:
The memory circuit device performs self-repair by incorporating the redundant decoder control circuit that can autonomously process the address of the failed storage line and activate redundant storage lines without requiring external controller intervention. This self-service mechanism reduces data transmission loads and improves repair efficiency.
2Ease of repair
If an external controller is used to store and analyze failed storage line information, then repair control can be achieved, but device complexity and data transmission requirements increase
Solution Approach 1:
The patent merges the repair control functionality into the memory circuit device by integrating the redundant decoder control circuit with the existing memory cell array and decoding circuits. This consolidation eliminates the need for separate external controller components and reduces the overall system complexity while maintaining ease of repair.
Solution Approach 2:
The redundant decoder control circuit serves multiple functions: it receives the address of the failed storage line from the testing device, decodes the address to identify the corresponding redundant storage line, and activates the redundant storage line for replacement. This multi-functional integration reduces the need for separate control components.
Data Source
AI summary
A memory circuit device and a memory test method are disclosed. The memory circuit device includes: a memory cell array, including storage lines and redundant storage lines; and a redundant decoder control circuit, configured to receive an address of a failed storage line from a testing device and activate a corresponding redundant storage line based on the address of the failed storage line, so that the redundant storage line can replace and store data in the failed storage line, wherein the address of the failed storage line is determined while testing operation status of the storage lines in the memory cell array. Embodiments of the present invention can improve repair efficiency of the memory circuit device through activating the associated redundant storage line by the redundant decoder control circuit based on the address of the failed storage line rather than under the control of an external controller.