Reference Bit Testing and Repair in Memory Built-In Self-Test
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Solution Overview
Problem
Conventional memory testing schemes fail to effectively detect and repair defects in reference bits, which can lead to failures in read operations affecting multiple data bits, and existing error-correcting code techniques struggle to handle complex defects associated with reference bits.
Innovation Solution
A memory-testing circuit that associates data bit columns with reference bit columns, performs read operations, compares outputs with good-machine values, and uses repair circuitry to replace defective reference bit columns, allowing for the detection and repair of defects in reference bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test schemes are used to access data bits functionally, then data bit operations can be performed, but defects in reference bits cannot be detected
Solution Approach 1:
The patent introduces an intermediary testing mechanism that temporarily associates data bit columns with alternative reference bit columns during test mode. This intermediary association allows the test system to detect reference bit defects by comparing read operations using different reference bits, without requiring fundamental changes to the memory architecture or operational complexity.
2Productivity
If reference bit lines are frequently operated for read operations, then multiple data bits can be read, but the reference bit line becomes prone to failing
Solution Approach 1:
The patent changes the operational parameters of reference bit lines by implementing a testing regime that periodically switches between different reference bit columns. This parameter change allows the system to monitor reference bit health over time and detect degradation before it causes failures during normal high-throughput operations.
Solution Approach 2:
The patent performs preliminary testing of reference bit lines before they are fully utilized in production operations. By conducting read operations with alternative reference bit associations during test mode, the system identifies potential failures beforehand, preventing reference bit line failures during actual high-productivity operations.
3Reliability
If ECC techniques are used to fix permanent bit fail problems, then data bit errors can be corrected, but defects associated with reference bits cannot be detected
Solution Approach 1:
The patent segments the error detection and correction functions by separating data bit ECC operations from reference bit testing operations. While ECC continues to handle data bit errors, a dedicated testing mechanism segments the reference bit validation process, allowing independent detection and reporting of reference bit defects without interfering with data bit correction capabilities.
Data Source
AI summary
A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.