ECC Engine Defect Detection via Test Syndrome Comparison
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Solution Overview
Problem
Current semiconductor memory devices lack an effective method to detect defects in error correction code (ECC) engines, which is crucial for ensuring data integrity and reliability, especially in high-density 3D stacked memory structures.
Innovation Solution
Incorporating a test circuit within the semiconductor memory device that generates a test syndrome and an expected decoding status flag, allowing for the comparison with test parity data to determine if the ECC engine has a defect, using Reed-Solomon encoding and decoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test circuit is added to detect ECC engine defects, then reliability is improved, but device complexity increases
Solution Approach 1:
The test circuit is merged with the existing ECC engine structure, sharing common components such as the memory cell array, bit lines, and decoding logic. The test circuit utilizes the same hardware resources for both normal ECC operations and defect detection, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The test circuit is designed with multi-functionality, serving both as a defect detection mechanism and as part of the normal ECC operation system. The same circuit components perform different functions depending on the operational mode (normal mode vs. test mode), reducing the need for separate dedicated test hardware and thus limiting the increase in device complexity
2Measurement precision
If comprehensive testing of ECC engine is performed, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The test circuit performs preliminary defect detection by generating test syndromes and comparing them against expected values before actual data storage operations. This preliminary testing ensures that the ECC engine is functioning correctly in advance, improving measurement precision while minimizing time loss by catching defects early in the operational sequence
Solution Approach 2:
The test circuit implements a feedback mechanism where test syndromes are generated, compared with expected decoding status flags, and used to determine whether the ECC engine has defects. This feedback loop enables precise defect detection by continuously monitoring ECC operations and adjusting testing based on observed performance, achieving high measurement precision without excessive time loss through targeted rather than exhaustive testing
Data Source
AI summary
A semiconductor memory device includes a buffer die and a plurality of memory dies. Each of the memory dies includes a memory cell array, an error correction code (ECC) engine and a test circuit. The memory cell array includes a plurality of memory cell rows, each including a plurality of volatile memory cells. The test circuit, in a test mode, generates a test syndrome and an expected decoding status flag indicating error status of the test syndrome, receives test parity data generated by the ECC engine based on the test syndrome and a decoding status flag indicating error status of the test parity data, and determines whether the ECC engine has a defect based on comparison of the test syndrome and the test parity data and a comparison of the expected decoding status flag and the decoding status flag.