Back-to-Back Memory Chips on PCB via Center Layer Vias
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Solution Overview
Problem
The existing methods for connecting memory chips to a CPU on a Printed Circuit Board (PCB) face challenges such as increased signal transmission line effects due to T-branch topology, which limits signal speed and requires more space, especially as the number of memory chips increases, and current solutions like mirrored RAM chips are not commercially available.
Innovation Solution
A memory arrangement where two symmetrical memory chips are placed back to back on opposite surfaces of the PCB, with respective pins connected by Plated Through vias to signal traces on a center layer, reducing the need for T-branches and ensuring symmetrical signal trace lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If T-branch topology is used to connect memory chips to CPU, then all pins can be connected, but signal transmission line effects increase and signal speed is limited
Solution Approach 1:
The patent transitions from a 2D surface mounting approach to a 3D stacked architecture where memory chips are placed on both sides of the PCB and connected through vias to a center layer. This dimensional change eliminates the T-branch topology and creates direct point-to-point connections, reducing signal path length and transmission line effects while maintaining full pin connectivity.
Solution Approach 2:
Instead of routing all signals from one side of the PCB (conventional approach), the patent inverts the connection architecture by placing memory chips on both sides and routing critical signals through the center layer via vias. This inversion creates symmetrical signal paths and eliminates the inherent asymmetry and stubs of T-branch topology.
2Reliability
If T-branch topology is used to connect memory chips, then all pins can be connected, but PCB area requirements increase
Solution Approach 1:
By utilizing the third dimension (via connections through the PCB thickness) and placing memory chips on both sides of the board, the patent compactly routes connections vertically through the center layer rather than sprawling horizontally across the PCB surface. This dramatically reduces the required PCB area while maintaining complete pin connectivity.
3Manufacturing precision
If mirrored RAM chips are used on both sides of PCB, then signal trace length can be equalized, but via length creates timing difference
Solution Approach 1:
The patent merges the connection paths of both memory chips to the center layer through symmetrical via placements. By connecting corresponding pins from both sides to the same center layer signal traces, the total signal path lengths are equalized, compensating for the via length difference and achieving timing synchronization.
4Quantity of substance
If more memory chips with many pins are used, then memory capacity increases, but fitting all connecting lines in limited PCB area becomes challenging
Solution Approach 1:
The patent utilizes the vertical dimension through vias and the dual-sided PCB architecture to route connections compactly. This allows high-density memory configurations with many pins per chip to be implemented without proportionally increasing PCB area, as connections are routed through the board thickness rather than across the surface.
Data Source
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AI summary
A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (M1, M2) arranged on a Printed Circuit Board, PCB. A first memory chip (M1) is arranged on a first surface of the PCB, a second memory chip (M2) is arranged on a second surface of the PCB. The second memory chip (M2) is placed back to back to the first memory chip (M1) and oriented such that respective pins having the same function on the first memory chip (M1) and the second memory chip (M2) are placed opposite to each other and connected by vias to respective signal traces arranged between the first and second surfaces of the PCB.