Back-to-Back Test Circuit for Cascaded Converter Switching Cells
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Solution Overview
Problem
Testing semiconductor devices of turn-off type for cascaded multi-level converters is complex and costly, making it difficult to ensure proper function under conditions similar to those in a cascaded multi-level converter without constructing a full converter system.
Innovation Solution
A back-to-back circuit with reduced number of switching cells and over-dimensioned inductance, compensated by capacitors at midpoints, allows for reliable testing of semiconductor devices with reduced complexity and cost, maintaining comparable ripple currents and impedance to a full cascaded multi-level converter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full cascaded multi-level converter system is constructed for testing semiconductor devices, then testing reliability is improved, but device complexity and cost increase significantly
Solution Approach 1:
The patent segments the full cascaded multi-level converter system into a simplified test arrangement that uses only a reduced number of switching cells (e.g., 2-4 cells instead of 8-16 cells). This segmentation allows testing of semiconductor devices without requiring the complete converter system, thereby reducing complexity while maintaining testing reliability through representative test conditions.
Solution Approach 2:
The patent creates a simplified copy of the actual converter system by using a reduced number of switching cells that replicate the essential electrical characteristics and operating conditions. This copy is sufficient for testing semiconductor devices without needing the full-scale system, thus reducing complexity while preserving testing validity.
2Device complexity
If the number of switching cells is reduced in the test arrangement, then device complexity and cost are reduced, but ripple current characteristics may deviate from actual converter conditions
Solution Approach 1:
The patent compensates for the reduced number of switching cells by adjusting key electrical parameters: using over-dimensioned inductance values (L ≥ 5 mH, preferably L ≥ 10 mH) and appropriately selected capacitance values. These parameter changes ensure that ripple current characteristics and impedance levels remain representative of actual converter conditions despite the simplified cell configuration.
Solution Approach 2:
The patent uses composite electrical characteristics by combining over-dimensioned inductance with specific capacitance values to create an equivalent electrical behavior that mimics the ripple current characteristics of a full-scale converter with many switching cells, thereby maintaining test accuracy with reduced complexity.
3Reliability
If inductance means are over-dimensioned in the test arrangement, then ripple current characteristics are improved, but fundamental frequency impedance increases
Solution Approach 1:
The patent carefully selects inductance values that are over-dimensioned relative to actual converter conditions (L ≥ 5 mH, preferably L ≥ 10 mH) to ensure adequate ripple current characteristics for testing. This parameter selection balances the need for representative ripple currents with acceptable impedance levels for proper device operation and measurement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The test arrangement enables reliable and cost-effective testing of semiconductor devices, reducing the number of switching cells needed while maintaining suitable currents for proper function evaluation, thus simplifying the testing process without compromising results.
Implementation Method 1
at least one capacitor (25) is arranged in an interconnection between the two midpoints (26, 27)
Implementation Method 2
inductance means (22) with an inductance of substantially the same magnitude as that of an inductance means in a phase leg of the cascaded multi-level converter
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
A test arrangement for testing the function of a switching cell (7, 7') configured to be a component of a cascaded multi-level converter and having at least one energy storing capacitor (21 ) comprises a so-called back-to-back circuit having such said switching cells connected in series in two phase legs (23, 24) interconnected through a mid point (26, 27) of the respective phase leg. The number of switching cells in each phase leg of the arrangement is reduced with respect to the number of switching cells intended to be connected in series in a phase leg of a said cascaded multi-level converter for which the switching cells are designed. Each of the two phase legs of the arrangement has inductance means with an inductance of substantially the same magnitude as that of the inductance means in said phase leg of a said cascaded multi-level converter. At least one capacitor (25) is arranged in said interconnection. Means (13) are configured to control the semi- conductor devices of the switching cells for changing switching state thereof and means (28) are arranged for measuring the current through said phase legs of the arrangement upon such control.