Back-to-Front Via Process for Semiconductor Chip Stacking
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Solution Overview
Problem
Current methods for forming electrical connections through electronic chips are challenging due to difficulties in precision and repeatability, especially when vias are deep, narrow, or close together, and are unsuitable for active semiconductor chips, leading to issues with signal cross-talk, capacitance, and resistance, particularly at high frequencies.
Innovation Solution
A process involving creating vias through a semiconductor chip or substrate with electrically conductive materials to form chip-to-chip connections, allowing for deep and narrow vias with controlled capacitance and resistance, and enabling stacking of chips with tight spacing without damaging the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via processes are used on active semiconductor chips, then electrical connections can be formed, but the chips are damaged and yield is reduced
Solution Approach 1:
The patent performs via formation, insulation deposition, and conductor filling processes before the chips are fully assembled and packaged. This preliminary action allows the use of specialized processes that would be impossible or damaging to perform on completed chips, while still achieving the desired electrical connections through the chips.
Solution Approach 2:
The patent divides the manufacturing process into distinct stages: chip fabrication, via formation through substrate, conductor filling, insulation deposition, and final chip assembly. This segmentation allows each process to be optimized independently, enabling complex via structures to be formed without damaging the active chip components.
2Object-generated harmful factors
If deep and narrow vias are used for chip connections, then signal cross-talk is reduced, but manufacturing precision and repeatability become nearly impossible
Solution Approach 1:
The patent introduces an insulating material as an intermediary between the conductor filling the via and the surrounding environment. This insulator enables the formation of deep, narrow vias with precise dimensions by providing lateral support and defining the via walls, making the via formation process repeatable and manufacturable.
Solution Approach 2:
The patent changes the physical and chemical parameters of the via structure by depositing insulating materials with specific dielectric properties and controlling their thickness precisely. This allows deep and narrow vias to be formed with controlled dimensions and electrical characteristics, achieving both low cross-talk and manufacturing precision.
3Reliability
If vias pass through charged semiconductor material, then electrical connections are achieved, but capacitance and resistance problems occur at high frequencies
Solution Approach 1:
The patent uses insulating materials as intermediaries between the conductive via and the charged semiconductor material. This insulation layer electrically isolates the via conductor from the charged chip regions, eliminating unwanted capacitance and resistance effects while maintaining the necessary electrical connection through the substrate.
Solution Approach 2:
The patent applies insulating materials selectively in specific locations around the via conductors where they contact or approach charged semiconductor regions. This localized insulation provides the necessary electrical isolation to control capacitance and resistance without affecting other parts of the chip structure.
4Ease of manufacture
If large packaging is used for chip-to-chip connections, then assembly is simplified, but packaging size and cost increase
Solution Approach 1:
The patent merges multiple functions into the substrate structure: mechanical support, electrical isolation, conductor routing, and alignment features are all integrated into the single substrate component. This consolidation eliminates the need for separate packaging elements, reducing overall packaging area while maintaining assembly simplicity.
Solution Approach 2:
The substrate is designed to perform multiple functions simultaneously: it provides structural support for the chips, forms the via walls for electrical connections, provides insulation between conductors, and enables alignment during assembly. This multi-functionality reduces the need for additional packaging components and reduces overall packaging size.
Data Source
AI summary
A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.