Backend Double-Walled Capacitors for IC Area Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional metal-insulator-metal (MIM) capacitors require a significant surface area to achieve desired capacitance, which is a challenge in densely packed integrated circuits where space is limited.
Innovation Solution
The implementation of backend double-walled capacitors (DWCs) with alternating dielectric and metal layers, which provide increased capacitance while occupying a smaller area, are integrated into interconnect layers of integrated circuit structures, allowing for more efficient electrical signal routing and power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MIM capacitors are used to achieve desired capacitance, then the capacitance performance is maintained, but the surface area occupied is significant
Solution Approach 1:
The patent implements a nested capacitor structure where an inner capacitor is formed within the same footprint as an outer capacitor. The inner capacitor consists of an inner first electrode, inner dielectric layer, and inner second electrode, all nested within the region occupied by the outer capacitor components. This nesting arrangement enables two capacitors to share the same planar area, effectively doubling the capacitance density without increasing the overall device footprint.
Solution Approach 2:
The patent transitions from a two-dimensional planar capacitor layout to a three-dimensional stacked configuration. By forming electrodes and dielectric layers in multiple vertical layers (first interconnect layer, second interconnect layer, third interconnect layer), the capacitor structure exploits the vertical dimension to increase capacitance. The alternating stacking of conductive layers and dielectric layers creates multiple capacitor elements that occupy the same horizontal footprint but are separated vertically, thereby achieving higher capacitance in a compact area.
2Productivity
If feature size is scaled down to increase device density, then the number of devices per chip increases, but the capacitance performance of each device deteriorates
Solution Approach 1:
The patent addresses the capacitance degradation at scaled dimensions by moving to a three-dimensional capacitor architecture. Instead of relying solely on lateral electrode area, the design stacks multiple dielectric and electrode layers vertically to create high-capacitance structures within a small footprint. This vertical stacking enables sufficient capacitance values to be achieved even when individual device features are scaled down, thereby maintaining capacitance performance while increasing overall device density.
Solution Approach 2:
The patent employs composite capacitor structures combining multiple dielectric materials with different properties. The first dielectric layer and second dielectric layer can have different dielectric constants and material compositions, allowing optimization of the overall capacitance. By using high-k dielectric materials in strategic positions and combining them with standard dielectrics, the structure achieves enhanced capacitance density that compensates for the reduced device area available at scaled dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables greater capacitance with reduced area usage, enhancing the performance and density of integrated circuits by providing effective electrical signal routing and power distribution in densely packed IC environments.
Implementation Method 1
double-walled capacitors (DWCs) with alternating dielectric and metal layers, which provide increased capacitance
Implementation Method 2
MIM capacitors have an insulator sandwiched between two metal plates
Data Source
Figure 1A~1D
Figure 2A~2C
Figure 3
AI summary
An integrated circuit (IC) structure having a plurality of backend double-walled capacitors (DWCs) are described. In an example, a first interconnect layer is disposed over a substrate and a second interconnect layer is disposed over the first interconnect layer. In the example, a plurality of DWCs are disposed in the first interconnect layer or the second interconnect layer to provide capacitance to assist the first interconnect layer and the second interconnect layer in providing electrical signal routing and power distribution to one or more devices in the IC structure. In examples, the IC structure includes a logic IC or a coupling substrate.