Electrical Backplane FEC Using Compressed Sync Headers
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Solution Overview
Problem
High-speed communication systems, such as Gigabit Ethernet networks, experience increased error rates due to higher throughput, leading to a need for error correction techniques that often result in additional overhead, which can decrease effective throughput.
Innovation Solution
Implementing a forward error correction (FEC) sublayer that compresses a two-bit synchronization header to a single bit, using one bit to send error detection or correction information, thereby reducing bit error rates without increasing communication overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward error correction is implemented to decrease error rates, then reliability is improved, but overhead increases which decreases productivity
Solution Approach 1:
The patent combines the synchronization header function and error detection function into a single integrated mechanism. The 64b/66b encoding scheme merges data bits with synchronization and error detection capabilities, eliminating the need for separate overhead bytes for these functions. This merging reduces total overhead while maintaining both synchronization accuracy and error detection capability.
Solution Approach 2:
The encoding scheme provides multi-functionality by using the same transmitted bits for multiple purposes: data transmission, synchronization indication, and error detection. The first bit of each 66b block serves as a synchronization indicator while all bits participate in error detection through the encoding scheme, making the system more efficient without requiring dedicated overhead for each function.
2Reliability
If additional error correcting information is communicated, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges error detection and synchronization functions into the existing data encoding structure. By using 64b/66b encoding where the first bit indicates synchronization state and the entire block participates in error detection, the system avoids adding separate error correction overhead. This merging approach maintains reliability while reducing device complexity compared to traditional separate overhead schemes.
Data Source
AI summary
Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.