Energy Efficient ICT TRIZ Cases
- Media Processor Clock Gating for Stable Power Demand
By tracking processing cycles and performance demand, clock gating smooths power peaks and protects media processors from thermal stress.
- Outphasing RF Transmitter Architecture for Low-Power High-Rate Signals
By splitting one non-constant envelope IF signal into two constant-envelope paths, this RF transmitter cuts PA power use and interference.
- Bus Clock Handover Timing for Conflict-Free Signal Transfer
Timed bus clock handover keeps the conductor driven during source switching, preventing conflicts, spurious pulses, and disrupted data transfer.
- Electrical Backplane FEC Using Compressed Sync Headers
A backplane FEC sublayer compresses a two-bit sync header to one bit, cutting error rates without adding throughput-reducing overhead.
- Wireless LAN Interference Detection Without Rate Fallback
By combining ED threshold checks with Ack errors, this case detects interference and avoids harmful rate fallback by raising retransmissions.
- Data-Driven Clock Gating for Fine-Grained VLSI Power Control
Local FIFO and processing-state monitoring gates the clock instantly, cutting dynamic VLSI power without software timing overhead.
- Memory Access Clocking Without a Local Oscillator
Bus-derived clock generation keeps memory access running while the local oscillator is powered down to cut IC power use.
- PLL Clock Gating Without Separate Control Clock in Deep Sleep
Power-save acknowledge and PLL disable signals gate clock distribution in deep sleep, cutting microprocessor power without a separate control clock.
- Tiled Reconfigurable Circuitry for Parallel Processing Bottlenecks
A tiled processor-switch-logic architecture improves parallel data transfer and reconfigurable computing without ASIC cost or FPGA power penalties.
- Data Bus Inversion Encoding for ISI and Crosstalk Control
Selective DBI algorithms invert parallel bus data when transitions spike, reducing ISI, crosstalk, SSN, and unnecessary power use.
- Predictive Clock Frequency Balancing Under Power Supply Constraints
A regulation circuit predicts workload shifts and rebalances clock frequencies to maintain processing speed without exceeding power limits.
- I/O Pin State Retention During CPU Core Power-Down Sleep
Stores and holds I/O pin values before CPU core sleep, cutting standby power while keeping peripheral signals asserted for fast wake-up.
- Transceiver Signal Amplitude Control for Low-Power IEEE 1394b Links
Adaptive transceiver amplitude control cuts IEEE 1394b link power use and electromagnetic noise while preserving stable communication.
- STBC Signal Decoding with Reduced ML Detection Complexity
By separating the real equivalent channel into a unit matrix and subchannel, STBC decoding cuts ML complexity, power use, and BER.