Bus Clock Handover Timing for Conflict-Free Signal Transfer
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Solution Overview
Problem
In portable equipment, the need for a common clock signal for multiple bus circuits increases power consumption and can lead to driving conflicts, especially when different bus circuits require different clock signals, resulting in spurious or missing clock pulses that disrupt operation.
Innovation Solution
Implementing a mechanism for clock control handover between different bus circuits, where driver circuits drive the clock conductor to a predetermined voltage level during specific time intervals, ensuring no floating state and preventing conflicting driving conditions, allowing for the use of push-pull driving circuits instead of wired logic, and enabling seamless transitions between clock sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common clock circuit with push-pull driver is used for all bus circuits, then clock signal distribution is simplified, but power consumption increases significantly
Solution Approach 1:
The patent extracts the clock signal generation function from a centralized common clock circuit and distributes it to individual bus circuits. Each bus circuit generates its own clock signal locally, eliminating the need for a power-consuming common push-pull driver while maintaining simplified clock distribution through the bus architecture.
2Use of energy by moving object
If different bus circuits generate their own clock signals, then power consumption is reduced, but driving conflicts may arise on the clock conductor
Solution Approach 1:
The patent implements preliminary action by establishing clear arbitration rules and handover protocols before clock signal conflicts can occur. Bus circuits follow predefined procedures to determine which circuit generates the clock signal at any given time, preventing driving conflicts before they arise and ensuring continuous stable clock signal generation.
3Adaptability or versatility
If wired logic circuits are used for clock generation, then multiple bus circuits can share the clock conductor, but the circuit speed slows down and power supply consumption increases
Solution Approach 1:
The patent replaces the mechanical/wired logic approach with electronic push-pull driver circuits that can actively drive the clock conductor. This substitution enables faster signal transitions and reduced power consumption while maintaining the ability of multiple bus circuits to share the clock conductor through controlled handover mechanisms.
4Use of energy by moving object
If clock control is handed over between different circuits, then power saving is enabled by switching circuits to sleep mode, but complex handover control is required
Solution Approach 1:
The patent implements self-service by enabling bus circuits to autonomously determine when to take over clock signal generation based on predefined arbitration rules. Each circuit can independently transition to active clock generation mode when conditions are met, eliminating the need for complex centralized handover control while enabling power-saving sleep modes for inactive circuits.
Data Source
AI summary
Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period following the start of execution of the handover command and to continue driving the clock conductor (10a) to the predetermined voltage level for a first time-interval. The clock conductor (10a) is driven to the predetermined voltage level with the driver circuit of the second circuit after a second time interval following the start of execution of the handover command until a third time interval has elapsed following the end of the second time interval. Subsequently the clock conductor (10a) is driven under control of the clock circuit (140) of the second circuit (14). The first time interval contains a first integer number P1 of periods of a first clock signal of the first circuit and the second and third time interval contain a second and third integer number P2, P3 of periods of a second clock signal of the second circuit, a duration corresponding to the second integer number P2 equaling at least a pulse duration of the first clock signal, a duration corresponding to the first integer number P1 equaling at least a duration corresponding to the second integer number P2 plus one, a duration corresponding to the second plus third integer P2, P3 equaling at least a duration corresponding to the first number P1 plus one.