Cache Line Retention for Atomic Instructions
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Solution Overview
Problem
In processors, simultaneous retired store operations can lead to cache conflicts and inefficient thrashing, wasting resources and power due to the eviction of memory lines, as multiple operations compete for cache storage.
Innovation Solution
A method and apparatus that store atomic instructions in a queue and identify target memory locations for load and store operations, acquiring and re-acquiring memory lines in the cache based on the atomic instruction's status in the queue, preventing unnecessary reacquisitions and reducing thrashing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple store operations simultaneously request cache lines, then cache storage capacity is exceeded, but cache thrashing and resource waste occur
Solution Approach 1:
The patent applies preliminary action by proactively retaining cache lines in the cache for atomic instructions before they are actually needed. When an atomic instruction is identified, its target cache line is retained in the cache even if other operations might normally evict it. This preliminary retention prevents future cache misses and thrashing, eliminating the need for repeated reacquisitions and reducing power consumption.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a special cache retention logic that acts as a mediator between the cache replacement policy and atomic instructions. This intermediary monitors which instructions are atomic and protects their target cache lines from eviction, effectively mediating between the limited cache capacity and the needs of atomic operations to prevent thrashing.
2Productivity
If cache lines are frequently evicted and re-acquired, then cache utilization is maximized, but processing efficiency decreases due to thrashing
Solution Approach 1:
The system performs preliminary action by pre-retaining cache lines associated with atomic instructions before they are evicted by normal cache replacement policies. This ensures that when atomic instructions need to access their target cache lines, the lines are already present in the cache, eliminating reacquisition delays and preventing thrashing.
Solution Approach 2:
The patent implements feedback by continuously monitoring the instruction queue to identify atomic instructions and their target cache lines. This feedback mechanism allows the cache retention logic to dynamically adjust which cache lines should be protected from eviction, ensuring that cache resources are allocated efficiently to atomic operations that require them.
3Device complexity
If normal cache replacement policy is used, then cache memory is efficiently managed, but atomic instructions suffer from cache misses and thrashing
Solution Approach 1:
The patent applies local quality by treating atomic instructions differently from normal instructions in the cache management system. Instead of applying a uniform cache replacement policy to all instructions, the system identifies atomic instructions and provides them with special protection for their target cache lines. This localized special treatment ensures that atomic operations have reliable cache access while maintaining efficient overall cache management.
Solution Approach 2:
An intermediary retention mechanism is introduced that sits between the normal cache replacement policy and the cache lines themselves. This intermediary monitors which cache lines are needed by atomic instructions and protects them from eviction, effectively mediating between the simple LRU replacement policy and the reliability needs of atomic operations.
Data Source
AI summary
A method and apparatus for controlling re-acquiring lines of memory in a cache is provided. The method comprises storing at least one atomic instruction in a queue in response to the atomic instruction being retired, and identifying a target memory location associated with load and store portions of the atomic instruction. A line of memory associated with the target memory location is acquired and stored in a cache. Subsequently, if the line of acquired memory is evicted, then it is re-acquired in response to the atomic instruction becoming the oldest instruction stored in the queue. The apparatus comprises a queue and a cache. The queue is adapted for storing at least one atomic instruction in response to the atomic instruction being retired. A target memory location is associated with load and store portions of the atomic instruction. The cache is adapted for acquiring a line of memory associated with the target memory location, storing the line of acquired memory in a cache, evicting the acquired line of memory from the cache in response to detecting a conflict regarding the acquired line of memory, and re-acquiring the line of memory in response to the atomic instruction becoming the oldest instruction stored in the queue.