Clock Control Circuit for Reducing Power Consumption in Semiconductor Memory

Solution Overview

Problem

Semiconductor memory devices with clock repeaters consume excessive power due to continuous operation of input and output control clock signals, which is problematic for mobile products that require long-term low-power operation.

Innovation Solution

A clock control circuit that generates input or output control clock signals only during data input or output operations, utilizing a clock generator and clock latency control circuit to synchronize with internal write enable, address valid, and chip select signals, reducing unnecessary power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the clock repeater continuously outputs input control clock signal and output control clock signal, then the data input buffer and data output buffer can continuously operate, but the current consumption increases significantly

Engineering Contradiction:

Improvecontinuous operation capabilityVSAvoidcurrent consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies periodic action by controlling the clock repeater to output clock signals only during specific periods when data input or output operations are required. The control logic circuit generates control signals based on operation mode signals (read/write commands) and timing signals (address valid signal, chip select signal) to enable the clock repeater only when needed, rather than continuous operation. This periodic activation significantly reduces current consumption while maintaining reliable data transfer functionality.

Inventive Principle:

Principle #19Periodic action

2Power

If the transistors in the clock repeater have high current driving ability, then the clock signals can be supplied to the data buffers, but unnecessary current is consumed when data is not being transferred

Engineering Contradiction:

Improvecurrent driving abilityVSAvoidunnecessary current consumption

Core Design Contradiction:

PowerVSLoss of energy

Solution Approach 1:

The patent applies dynamics by making the clock repeater's operation dynamic rather than static. The clock repeater's enable signal is dynamically controlled by the control logic circuit based on real-time operation conditions (read/write mode, address validity, chip select status). This dynamic control allows the high-current-capable transistors to be activated only when data transfer is required, eliminating unnecessary current consumption during idle periods while maintaining the power driving ability needed for reliable clock signal supply to the data buffers.

Inventive Principle:

Principle #15Dynamics

3Productivity

If the data input buffer and data output buffer operate continuously in response to toggled clock signals, then data can be transferred at any time, but power consumption increases during idle periods

Engineering Contradiction:

Improvedata transfer capabilityVSAvoidpower consumption during idle periods

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The patent applies periodic action by controlling the clock repeater to output clock signals only during specific periods when data input or output operations are required. The control logic circuit generates control signals based on operation mode signals (read/write commands) and timing signals (address valid signal, chip select signal) to enable the clock repeater only when needed, rather than continuous operation. This periodic activation significantly reduces current consumption while maintaining reliable data transfer functionality.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS7324404B2Clock control circuit for reducing consumption current in data input and output operations and semiconductor memory device including the same and data input and output operations methods of semiconductor memory device

Publication Date: 2008.01.29 SK HYNIX INC

AI summary

The present invention relates to a clock control circuit, it can reduce power consumption in data input and output operations, and a semiconductor memory device including the clock control circuit, and data input and output operation method of the semiconductor memory device. The clock control circuit according to the present invention can generate an input or output control clock signal only when data are substantially input or output in the data input and output operations. It is thus possible to save unnecessary power consumption.