PLL Clock Gating Without Separate Control Clock in Deep Sleep
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Solution Overview
Problem
Conventional clock distribution systems in microprocessors face challenges in reducing power consumption due to the need for a separate clock for control logic, which complicates design, integration, and signal synchronization, especially when attempting to gate off clock distribution during deep power saving modes.
Innovation Solution
A method that disables the Phased Locked Loop (PLL) and gates clock distribution by generating power mode signals, allowing the PLL to be controlled without a separate clock, using a combination of power save mode acknowledge and PLL disable signals to manage clock distribution, enabling power saving without a separate clock distribution system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a separate clock distribution is used for control logic to enable deep power saving mode, then power consumption is reduced, but design complexity increases and integration becomes difficult
Solution Approach 1:
The patent merges the control logic clock with the main clock distribution network by using a shared clock signal that can be selectively gated. The pervasive logic and power management functions share the same clock distribution infrastructure, eliminating the need for a separate clock network while maintaining the ability to gate clock distribution for power saving.
Solution Approach 2:
The clock distribution system is designed to serve multiple functions: it provides clock signals to both the main logic and the power management control logic simultaneously. The pervasive logic can operate in different modes (full operation, gated, or disabled) while sharing the same clock infrastructure, making the system more versatile and reducing overall complexity.
2Adaptability or versatility
If a separate clock distribution is used for control logic, then power management functions can operate independently, but signal synchronization becomes difficult due to asynchronous operation
Solution Approach 1:
By merging the control logic clock with the main clock distribution, the patent ensures that all logic elements operate synchronously on the same clock domain. This eliminates asynchronous signal crossing issues while still allowing independent power management through selective clock gating of different logic blocks.
Solution Approach 2:
The patent introduces clock gating mechanisms as intermediaries that selectively enable or disable clock signals to different logic blocks. This allows independent operation of power management functions while maintaining synchronous operation through the shared clock infrastructure, avoiding direct asynchronous connections.
3Loss of energy
If clock distribution is gated off during deep power saving mode, then power consumption is reduced, but control logic requires a separate clock to function
Solution Approach 1:
The patent implements dynamic clock gating where the clock distribution to pervasive logic is selectively enabled or disabled based on the power mode. During deep power saving mode, the clock is gated off to reduce power consumption, while during active modes, the clock is enabled to allow full operation, providing dynamic adaptability without requiring separate clock networks.
Solution Approach 2:
The power management logic uses the same clock distribution network it helps to control. The pervasive logic can monitor its own clock signal and autonomously enter low-power states by gating its own clock input, eliminating the need for external separate clocking infrastructure while maintaining self-management capability.
Data Source
AI summary
An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.