Semiconductor IC Desynchronized Initialization Clock Control

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Solution Overview

Problem

Existing semiconductor integrated circuits face high instantaneous power consumption during initialization due to synchronized clock supply operations across multiple power domains, which cannot be effectively mitigated by existing techniques.

Innovation Solution

A semiconductor integrated circuit with a power control unit and an initialization control unit that delays the start of clock supply for one power domain relative to another, allowing for desynchronized initialization and reducing peak power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If synchronized clock supply operations are used for multiple power domains during initialization, then initialization can be performed efficiently with simple control, but instantaneous power consumption concentrates and increases significantly

Engineering Contradiction:
Improveinitialization efficiencyVSAvoidinstantaneous power consumption
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The patent segments the initialization process across multiple power domains by introducing an initialization control unit that independently manages clock supply timing for each domain. Instead of synchronized initialization, the system divides the initialization task and executes them sequentially or with time offsets, preventing power concentration while maintaining initialization completeness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies dynamic control of clock supply timing through the initialization control unit. The system adjusts the timing of clock supply to different power domains based on their individual initialization states, using flexible timing control to spread out power consumption peaks and achieve balanced power distribution during initialization.

Inventive Principle:
Principle #15Dynamics

2Power

If desynchronized clock supply is implemented for multiple power domains, then peak power consumption is reduced, but initialization control complexity increases

Engineering Contradiction:
Improvepeak power consumptionVSAvoidinitialization control complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent introduces an initialization control unit as an intermediary component that manages the desynchronized clock supply operations. This dedicated control unit handles the timing coordination between multiple power domains, centralizing the complexity in a single component while keeping the overall system architecture clean and manageable.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of energy

If power is shut down to multiple power domains simultaneously, then overall power consumption is reduced, but concentration of power consumption occurs during simultaneous initialization

Engineering Contradiction:
Improveoverall power consumptionVSAvoidconcentration of power consumption
Core Design Contradiction:
Loss of energyVSPower

Solution Approach 1:

The patent applies preliminary action by having the initialization control unit prepare and coordinate clock supply timing before actual initialization begins. The system pre-plans the timing sequence for different power domains, ensuring that clock supply is distributed in a way that prevents power concentration while maintaining efficient initialization progression.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9360921B2Semiconductor integrated circuit, information processing apparatus, and control method
Publication Date: 2016.06.07 CANON KK
  • US9360921B2 patent drawing
  • US9360921B2 patent drawing
  • US9360921B2 patent drawing

AI summary

In a system large-scale integration (LSI) including a plurality of subsystems having a power shutdown mechanism, sometimes instantaneous power consumption of the LSI intensively increases at timing of supplying a clock for initialization due to a shift of a power mode of a subsystem. After power supply starts to return to a first subsystem and a second subsystem, an increase in power consumption during initialization is distributed by desynchronizing timing of clock supply to start initialization for the first subsystem and the second subsystem.