Data-Driven Clock Gating for Fine-Grained VLSI Power Control
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Solution Overview
Problem
In modern VLSI designs, clock power consumption is significant due to increasing power leakage, and conventional clock gating techniques are inefficient in reducing dynamic power consumption, especially as they require software intervention and cannot effectively gate the clock signal in desired time units.
Innovation Solution
A digital logic processing device with a clock controller circuit that monitors data presence and states of input FIFO and processing units, controlling the clock signal based on flag signals to enable instantaneous and software-independent clock gating, allowing for hard-wired streaming processing and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If software-controlled clock gating is used, then power consumption can be reduced, but the clock gating cannot be achieved at the desired time unit and the controlled unit becomes relatively large
Solution Approach 1:
The processing element autonomously controls its own clock signal based on local conditions (data availability in FIFO and processing unit state), eliminating the need for external software intervention. The clock controller circuit automatically gates the clock at the desired time unit by monitoring internal states and generating appropriate control signals.
Solution Approach 2:
The system divides the processing function into independent processing elements, each with its own clock controller circuit that can autonomously manage clock gating. This segmentation allows fine-grained control at the desired time unit without requiring software coordination across the entire system.
2Productivity
If clock signal is continuously supplied to processing elements, then processing operations can be performed without interruption, but dynamic power dissipation increases
Solution Approach 1:
The clock signal is supplied periodically rather than continuously - the clock controller circuit enables the clock signal when data is available and processing is needed, and gates (interrupts) the clock signal when the processing element is idle. This periodic clock supply maintains processing continuity when needed while eliminating unnecessary dynamic power dissipation during idle periods.
Data Source
AI summary
Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.