Memory Command Throttling via Synchronization

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Solution Overview

Problem

In multi-channel memory systems, power management techniques struggle to synchronize memory command throttling across independent memory channels, leading to memory access stalls and suboptimal power/performance duty-cycles due to out-of-phase throttling windows, which impact application performance and power consumption.

Innovation Solution

A synchronization command is introduced, allowing a master memory controller to coordinate memory controllers within an interleaved group, ensuring synchronized start times and widths of throttling windows through an N/M synchronization command, which includes a bit for each controller to forward the command to power control logic, ensuring deterministic power management across channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If independent memory controllers operate memory channels separately, then each controller can manage its channel independently, but throttling windows become out-of-phase causing memory access stalls and suboptimal power/performance duty-cycles

Engineering Contradiction:

ImproveIndependent memory channel managementVSAvoidMemory access throughput

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent merges the independent operation of multiple memory controllers with a centralized synchronization mechanism. A master memory controller coordinates throttling commands across all slave memory controllers, ensuring their throttling windows are aligned in phase. This combination maintains independent channel management while eliminating the performance degradation caused by out-of-phase throttling through synchronized command distribution and status bit coordination.

Inventive Principle:

Principle #5Merging (Combining)

2Use of energy by moving object

If memory power management is implemented, then power consumption is reduced, but memory access performance deteriorates due to throttling

Engineering Contradiction:

ImproveMemory power consumptionVSAvoidMemory access speed

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent implements periodic duty-cycle based throttling where memory controllers operate in alternating active and throttled states. By synchronizing these periodic actions across all memory channels, the system achieves coordinated power management that reduces overall power consumption while minimizing performance impact through predictable, aligned throttling windows rather than random or staggered interruptions.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The system dynamically adjusts memory controller operation between full performance mode and throttled power-saving mode based on system needs. The synchronization mechanism ensures that transitions between these dynamic states occur simultaneously across all channels, optimizing the balance between power consumption and performance by coordinating when throttling begins and ends across the entire memory subsystem.

Inventive Principle:

Principle #15Dynamics

3Productivity

If synchronization commands are implemented across multiple memory controllers, then throttling windows are aligned, but system complexity increases

Engineering Contradiction:

ImproveSynchronized memory operationVSAvoidMemory controller coordination

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the memory controller system into one master controller and multiple slave controllers, with the master handling synchronization logic. This segmentation concentrates the complexity of coordination in a single controller while allowing slave controllers to follow simple synchronized commands, thereby achieving coordinated operation without distributing complex synchronization logic across all controllers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The master memory controller acts as an intermediary between the system's power management needs and the individual memory channels. It receives synchronization commands, distributes them to slave controllers, and coordinates their operation, thereby simplifying the overall system architecture by centralizing the mediation function rather than requiring direct peer-to-peer coordination between all controllers.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8867304B2Command throttling for multi-channel duty-cycle based memory power management

Publication Date: 2014.10.21 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted. Each of the multiple memory controllers with the asserted associated synchronization indication then transmits the forwarded synchronization command to associated power control logic.