Integrated Circuit Power Control Block for Leakage Reduction
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Solution Overview
Problem
Conventional methods for reducing power consumption in integrated circuits, particularly in processors, are inadequate as they either partially address dynamic power consumption or rely on external microcontrollers, failing to effectively minimize both dynamic and leakage power consumption, especially in deep sub-micron processes.
Innovation Solution
An integrated circuit design with a power control block and a power management mechanism that allows the system core block to be powered down by a separate voltage supply, utilizing a digital logic circuit for power control logic, eliminating the need for an external microcontroller and reducing overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If frequency scaling is used to reduce power consumption, then dynamic power consumption is partially reduced, but leakage power consumption remains significant
Solution Approach 1:
The processor itself serves as the power control mechanism, using its own computational resources to manage power states. The processor can autonomously transition between active and low-power states based on workload requirements, eliminating the need for external microcontrollers while achieving both dynamic and leakage power reduction through self-managed clock gating and voltage scaling.
Solution Approach 2:
The patent employs dynamic voltage and frequency scaling (DVFS) to adjust operational parameters of the processor. By changing voltage levels and clock frequencies according to workload demands, the system optimizes the balance between performance and power consumption, effectively reducing both dynamic power (through frequency scaling) and leakage power (through voltage scaling and idle state management).
2Use of energy by moving object
If an external microcontroller is used to control power supply, then power consumption can be controlled, but device complexity and external component requirements increase
Solution Approach 1:
The patent merges the power control functionality directly into the processor by integrating a power management unit (PMU) and clock gating logic within the processor core. This consolidation eliminates the need for external microcontrollers or separate power management ICs, reducing device complexity while maintaining comprehensive power control capabilities for both dynamic and leakage power management.
Solution Approach 2:
The processor becomes self-sufficient in power management by incorporating internal logic that can autonomously control its own power states, clock signals, and voltage levels. This self-service approach eliminates external control dependencies, simplifying the overall system architecture while achieving effective power consumption control.
Data Source
AI summary
Power management methods for integrated circuits are disclosed. A system core block is disposed in a chip and comprises a central processing unit. A power control block is disposed in the chip and comprises a power management mechanism coupled to a power supply to control the supply of power to the system core block. The power management mechanism outputs a power down signal and stops supply of power to the system core block according to a power saving mode setting signal from the central processor unit and starts the supply of power to the system core block according to a power saving mode release signal.