I/O Pin State Retention During CPU Core Power-Down Sleep
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Solution Overview
Problem
Integrated circuits in portable devices face challenges in reducing standby power consumption while maintaining processor state integrity and avoiding burdensome trace routing requirements, especially when powering down CPUs and system-on-a-chip designs.
Innovation Solution
A circuit that maintains asserted values on input/output pins by using an interface to store current values before sleep mode and restore them upon waking, eliminating the need for multiple signals from a special power domain, thus reducing trace routing requirements and allowing seamless transitions between sleep and active modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the CPU core is powered down to reduce standby power consumption, then power savings are achieved, but processor state integrity is lost and wake-up response time increases
Solution Approach 1:
The patent segments the power domain by creating a special power domain that remains powered on while the CPU core enters deep sleep mode. This allows selective powering down of specific components (CPU core) while maintaining power supply to other components (special power domain containing IO pad control logic), thereby preserving processor state integrity and enabling fast wake-up without requiring full system power restoration.
2Reliability
If multiple signals are routed from the special power domain to each IO pad to maintain state, then processor state integrity is preserved, but trace routing complexity increases significantly
Solution Approach 1:
The patent merges multiple pad control signals into a single shared signal line that is common to all IO pads in the special power domain. Instead of routing separate control signals from the special power domain to each individual pad, a single shared signal is used to control all pads simultaneously, dramatically reducing the number of traces required while maintaining state integrity across all IO pads.
3Speed
If a special power domain is created to maintain IO pad state during deep sleep, then wake-up responsiveness is improved, but the distribution of power and routing of control signals becomes more complex
Solution Approach 1:
The patent creates a universal shared control signal that serves multiple functions: it controls the enable state of all IO pads simultaneously, provides wake-up capability, and maintains state integrity across all pads. This single multi-functional signal replaces what would otherwise require multiple separate control lines, simplifying the overall system architecture while achieving fast wake-up response.
Data Source
AI summary
In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.