Interrupt Controller Using Shared Bus and Hierarchical Tracking
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Solution Overview
Problem
Current interrupt handling systems face high implementation costs due to the need for multiple wires and complex register structures, and they struggle with level-sensitive interrupts and resource-intensive search processes.
Innovation Solution
A method and apparatus for interrupt collection and reporting that uses a status indicator register, assigns unique Interrupt Source Numbers (INTSNs), prioritizes arbitration requests, compresses INTSNs, and maps them onto an interrupt source control structure to efficiently manage and deliver interrupts to the appropriate entities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wire is required for each hardware or software entity to send interrupts, then interrupt signals can be directly transmitted, but implementation costs become potentially large
Solution Approach 1:
Multiple interrupt sources are merged into a single shared bus for transmitting interrupt signals. Instead of having dedicated wires for each entity, the patent uses a common interrupt bus where multiple sources can signal interrupts, significantly reducing the number of physical connections required while maintaining reliable interrupt transmission.
Solution Approach 2:
An intermediary interrupt controller is introduced between the interrupt sources and the processor. This controller manages the shared interrupt bus, arbitrates between multiple interrupt sources, and presents a simplified interface to the processor, thereby reducing implementation complexity while ensuring reliable interrupt handling.
2Loss of information
If generated interrupts are written into a wide register with bits for all possible interrupts, then all interrupts can be tracked, but the processor needs to spend resources and time to search through the wide register
Solution Approach 1:
The interrupt tracking functionality is segmented into multiple smaller registers or data structures organized in a tree structure. Instead of one large wide register, interrupts are divided into groups managed by separate smaller registers, allowing the processor to search through segmented structures more efficiently and reduce the time required to identify and handle specific interrupts.
Solution Approach 2:
The patent transforms the flat wide register structure into a hierarchical tree structure with multiple levels. This dimensional change allows interrupts to be organized in groups and subgroups, enabling the processor to navigate through the interrupt structure more efficiently by first identifying the group and then the specific interrupt within that group, thereby reducing search time.
3Measurement precision
If each hardware or software entity stores an interrupt number for each vector number, then interrupts can be identified, but implementation cost increases due to storage requirements
Solution Approach 1:
The patent implements a universal interrupt numbering scheme where a single interrupt number can represent multiple interrupt sources or vectors. Instead of requiring separate storage for each vector number, the system uses a unified interrupt identification mechanism that can map multiple sources to a common numbering space, reducing storage requirements while maintaining precise interrupt identification.
4Ease of operation
If level sensitive interrupts are not supported by conventional methods, then simpler interrupt handling is used, but the system cannot handle level-sensitive interrupt requirements
Solution Approach 1:
The interrupt handling system is made dynamic by implementing configurable interrupt controllers that can adapt to different interrupt types including level-sensitive interrupts. The system can dynamically adjust its behavior based on the interrupt source and type, supporting both edge-triggered and level-sensitive interrupt modes while maintaining ease of operation through automated configuration and management.
Data Source
AI summary
A method and a system embodying the method for interrupt collecting an reporting, comprising: storing for each of at least one interrupt a status indicator, an enable status, and an interrupt delivery information in a first structure; storing for each of the at least one interrupt at least an indicator of one or more entities to execute an interrupt handler routine in a second structure; and reporting one of the at least one interrupt to the one or more entities to execute an interrupt handler routine designated in accordance with the status indicator, the enable status, the interrupt delivery information, and the at least one indicator, is disclosed.