Backplane SerDes PAM-4 Full Duplex Transmission
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Solution Overview
Problem
Developing high-speed backplane systems with 40-inch lane length and reliable 10 Gbps/lane data rates is challenging due to stringent low noise requirements and technical difficulties, such as high bit error rates and crosstalk noise, which existing SerDes systems fail to meet.
Innovation Solution
Implementing a full duplex transmission method using two-bit pulse-amplitude modulation (PAM-4) in a backplane serializer/deserializer (SerDes) system, which allows for simultaneous data transfer in both directions over bidirectional links, reducing signaling speed without compromising throughput, and increasing data rates to meet the BER requirements for 40-inch multi-lane backplane systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional SerDes systems are used to achieve 10 Gbps/lane data rates over 40-inch backplane links, then high data rate transmission is enabled, but bit error rates increase and signal integrity deteriorates due to noise and crosstalk
Solution Approach 1:
The patent segments the transmission channel into multiple lanes and implements independent equalization for each lane. The equalizer divides the received signal into multiple components and processes them separately, allowing targeted compensation for interference in each segment while maintaining overall system reliability at high data rates
Solution Approach 2:
The patent implements a feedback mechanism where the equalizer continuously monitors the received signal quality and adjusts its coefficients dynamically. This feedback loop compensates for changing noise and crosstalk conditions, maintaining low bit error rates even when transmitting at 10 Gbps/lane over 40-inch backplane links
2Productivity
If signaling speed is increased to achieve higher throughput, then data transmission capacity improves, but noise and crosstalk increase causing signal integrity to deteriorate
Solution Approach 1:
The patent merges multiple transmission lanes into a unified full-duplex system where bidirectional traffic shares the same physical medium. By combining the transmission and reception paths and implementing joint equalization, the system achieves high throughput while consolidating noise management into a single coordinated process that prevents noise accumulation
Solution Approach 2:
The patent changes the equalization parameters dynamically based on the signaling speed and traffic conditions. The equalizer coefficients are adjusted in real-time to optimize signal quality at different data rates, allowing the system to maintain signal integrity whether operating at lower speeds for long distances or at higher speeds for maximum throughput
3Productivity
If full duplex mode is implemented to double data throughput per link, then transmission capacity increases, but system complexity increases due to bidirectional signal management
Solution Approach 1:
The patent implements a universal equalizer design that handles both unidirectional and bidirectional traffic patterns using the same core algorithm. The equalizer can operate in half-duplex or full-duplex mode without requiring separate processing paths, reducing system complexity while enabling full duplex operation to double throughput per link
Solution Approach 2:
The patent implements dynamic resource allocation where the equalizer adapts its processing intensity based on traffic conditions. During full duplex operation, the equalizer dynamically adjusts its coefficients for each direction independently, managing bidirectional signals efficiently without requiring static complex circuitry for every possible traffic scenario
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The full duplex transmission method doubles data throughput per link while maintaining the same signaling bandwidth, reducing bit error rates and extending the system's operational lifetime by supporting higher data rates and improving signal integrity, thus meeting the requirements for high-speed communications.
Implementation Method 1
employing two-bit pulse-amplitude modulation (PAM-4) to reduce signaling speed of the first bidirectional link and the second bidirectional link
Data Source
AI summary
A system for a backplane serializer/deserializer (SerDes) including first and second integrated circuits (IC). The first and second ICs include transmitters and receivers coupled to each other through first and second bidirectional links. A first receiver is configured to receive first data at a data rate on a first channel supported by both the first bidirectional link and the second bidirectional link. A second receiver is configured to receive second data at the data rate on a second channel supported by both the first bidirectional link and the second bidirectional link. The backplane SerDes is configured to transfer the first and second data in full duplex mode by employing two-bit pulse-amplitude modulation (PAM-4) to reduce signaling speed of the first and second bidirectional links without reducing throughput of a lane pair including the first and second channels.