Synchronisation Signal Speed/Phase Control TRIZ Cases
- Adaptive Channel Estimator Clock Phase Compensation
An adaptive channel estimator adjusts FIR filter tap weights to compensate clock phase corrections derived from Center of Filter offset calculations.
- Twisted Wire Pair Network Interface Power Management
A network interface device enters low power mode using a partial frame counter to time receiver activation windows.
- Heterogeneous Clock Management via Invariant TSC
A clock management circuit correlates core timing with a reference clock using invariant timestamp counters.
- Low-Power Serial Link Clock Division for Phase Lock Retention
Divides transmitter clock frequency to reduce power consumption while maintaining receiver phase lock, eliminating exit delays from re-locking sequences.
- Adaptive Correlation State Machine for Signal Processing
A state-based correlation method transitions between resolution levels to verify signal index values.
- Multi-Level Clock Data Recovery Circuit Amplitude Detection
A multi-level clock and data recovery circuit uses segmented samplers with independent reference offset voltage levels for precise signal detection.
- SCMA with LDPC FEC Coding for NOMA Systems
Scrambled coded multiple access uses low density parity check coding to enable asynchronous multi-user wireless channel sharing.