Heterogeneous Clock Management via Invariant TSC
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Solution Overview
Problem
Existing computer systems, particularly in automation and edge computing, face challenges in achieving precise time synchronization across multiple clocks, which is critical for maintaining accurate processing and communication within these systems.
Innovation Solution
The implementation of a heterogeneous clock management system that utilizes internal hardware features such as invariant time stamp counters, timed GPIO, and always-running timers to manage clock synchronization, eliminating the need for custom ASICs and reducing communication delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If custom ASICs are used to manage clock synchronization, then clock management precision can be improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the clock management function from custom ASICs and implements it using standard CPU instructions and existing hardware features. The time synchronization functionality is taken out of dedicated hardware and realized through software-based approaches using invariant TSC, timed GPIO, and always-running timers, thereby reducing device complexity while maintaining synchronization precision.
Solution Approach 2:
The patent replaces the mechanical/hardware-based clock management system (custom ASICs) with a software-based system running on general-purpose processors. By substituting dedicated hardware with software instructions and standard CPU features, the system achieves the same clock synchronization functionality with reduced complexity and improved adaptability.
2Measurement precision
If custom ASICs are used for clock management, then synchronization precision can be improved, but manufacturing cost and ease of manufacture worsen
Solution Approach 1:
The patent makes the clock management system universal by implementing it on standard processors that can be used across multiple platforms and applications. Instead of manufacturing custom ASICs for each specific application, the same processor architecture with software-based clock management can serve multiple purposes, greatly improving ease of manufacture and reducing production costs.
Solution Approach 2:
The patent replaces expensive custom ASICs with more economical standard processor components. By using invariant TSC, timed GPIO, and always-running timers that are already present in standard processors, the system achieves clock synchronization without requiring costly custom hardware manufacturing, thereby improving ease of manufacture.
3Loss of time
If external clock management components are used, then communication delays increase, but if integrated solutions are used, then manufacturing complexity increases
Solution Approach 1:
The patent merges the clock management functionality with the core processor by utilizing invariant TSC, timed GPIO, and always-running timers that are integrated into the CPU architecture. This consolidation eliminates external clock management components and the associated communication delays, while the merging is achieved through software configuration rather than complex hardware integration.
Solution Approach 2:
The patent introduces a clock management software layer as an intermediary that coordinates between the core processor and peripheral devices using standard CPU instructions and hardware features. This software intermediary manages timing synchronization without requiring complex hardware integration, thereby reducing both communication delays and integration complexity.
Data Source
AI summary
Systems and techniques for an heterogeneous clock management solution for industrial systems are described herein. In an example, a system includes a clock management circuit adapted to receive core timing information from a core of an integrated circuit. The clock management circuit is further adapted to correlate the core timing information with a reference clock. The clock management circuit is further adapted to output frequency and time offset of the reference clock to the core timing information. The system includes an execution circuit adapted to schedule a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset. The execution circuit is further adapted to issue a command to execute the transaction at the scheduled time.