Low-Power Serial Link Clock Division for Phase Lock Retention
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Solution Overview
Problem
Conventional high-speed serial links face challenges in achieving real power savings while minimizing entry and exit times from low-power modes, which can impact system performance due to prolonged entry and exit sequences and loss of phase lock on the receiver side.
Innovation Solution
The solution involves dividing the transmitter clock to operate at a lower rate during low-power mode, maintaining the same phase relationship as the undivided clock, allowing the receiver to maintain phase lock and reducing operation rates, thereby enabling quick entry and exit from low-power states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the receiver shuts down during low-power mode to save power, then power savings are achieved, but phase lock is lost and equalization/gain settings are lost requiring re-establishment on exit
Solution Approach 1:
The receiver preserves phase lock and equalization/gain settings during low-power mode by maintaining minimal operational state, rather than shutting down completely. This preliminary preservation of critical parameters eliminates the need for re-establishment upon exit, resolving the contradiction between power savings and exit time.
Solution Approach 2:
The receiver performs partial shutdown by maintaining essential functions (phase lock, equalization) while disabling non-essential functions. This selective maintenance allows the receiver to achieve significant power savings while avoiding complete loss of critical parameters, thus reducing exit time without requiring full operational status.
2Loss of energy
If the link fully enters low-power mode before exiting, then maximum power savings are achieved, but system performance is doubly affected if data traffic arrives during entry and exit sequences
Solution Approach 1:
The receiver preserves phase lock and settings during the low-power mode entry sequence, so that if data traffic arrives during entry or exit, the link can resume operation immediately without additional delay. This preliminary preservation eliminates the performance penalty that would otherwise occur from repeated re-locking.
Solution Approach 2:
By maintaining phase lock continuously through the low-power mode transition, the system ensures uninterrupted capability to process data traffic. The useful action of phase synchronization continues without interruption, preventing performance degradation even when data arrives during mode transitions.
3Use of energy by stationary object
If conventional low-power mode techniques shut down receive circuitry, then power is saved, but the receiver loses phase lock and equalization/gain settings requiring time to re-establish
Solution Approach 1:
The receive circuitry performs partial shutdown by maintaining essential functions (phase lock loop, equalization) while disabling non-essential functions. This selective maintenance preserves phase lock stability and setting integrity while achieving significant power reduction, resolving the contradiction between power consumption and reliability.
Solution Approach 2:
The system changes operational parameters by transitioning from full operation to a reduced-power state that maintains critical parameters (phase lock, equalization settings). This parameter change allows the receiver to operate in a low-power state without losing the reliability-critical phase lock, thus resolving the contradiction between power usage and phase lock stability.
Data Source
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AI summary
Systems and methods to provide a low-power mode for serial links are disclosed. One embodiment of such a system includes a transmitter coupled to a link; a receiver coupled to the link and configured to receive signals over the link from the transmitter; a transmit control module configured to cause the transmitter to enter and exit a low-power mode; and a clock module coupled to the transmitter and configured to provide a clock signal to the transmitter, wherein the clock module is further configured to provide the clock signal as a divided clock signal to the transmitter when the transmitter is in the low-power mode, further wherein the divided clock signal has a same phase as the clock signal before entry into the low-power mode.