Backside Bond Pads Under Memory Arrays Using TSV Connections
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Solution Overview
Problem
Conventional memory devices with bond pads located on the frontside of the memory array face issues of increased footprint and potential stress on the memory array, which can lead to damage during bonding operations.
Innovation Solution
The bond pad is relocated to the backside of the memory die with a through-silicon via (TSV) connecting it to the CMOS control circuitry, eliminating the need for extra wafer space and protecting the memory array from stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bond pads are located on the frontside of the memory array, then bonding operations can be performed, but the footprint increases and stress is applied to the memory array causing potential damage
Solution Approach 1:
The bond pads are relocated from the frontside (2D plane) to the backside of the memory die, utilizing the third dimension (depth/thickness) to resolve the conflict between bonding accessibility and footprint reduction. This dimensional transition allows bonding operations to proceed without occupying additional lateral space on the memory array surface.
Solution Approach 2:
Instead of placing bond pads on the conventional frontside of the memory die, the invention inverts the location to the backside. This inversion eliminates the need for extra wafer space and prevents stress on the memory array while maintaining bonding functionality through the substrate.
2Ease of manufacture
If bond pads are located on the frontside of the memory array, then bonding operations can be performed, but stress is applied to the memory array during bonding which can lead to damage
Solution Approach 1:
The bond pads are extracted from the memory array area and relocated to the backside of the substrate. This separation removes the source of stress from the memory array, preventing damage during bonding operations while maintaining the necessary electrical connections through the substrate via TSVs.
Solution Approach 2:
Through-silicon vias (TSVs) serve as intermediaries to connect the backside bond pads to the frontside memory array circuitry. This intermediary structure enables bonding operations on the backside while maintaining electrical functionality, effectively decoupling the bonding location from the memory array location.
3Ease of manufacture
If bond pads are located on the frontside of the memory array, then bonding operations can be performed, but extra wafer space is required
Solution Approach 1:
The bond pads are relocated from the frontside (2D plane) to the backside of the memory die, utilizing the third dimension (depth/thickness) to resolve the conflict between bonding accessibility and footprint reduction. This dimensional transition allows bonding operations to proceed without occupying additional lateral space on the memory array surface.
Solution Approach 2:
The backside of the substrate serves multiple functions: it provides the bonding surface for bond pads and simultaneously acts as the structural substrate that protects and supports the frontside memory array. This multi-functionality eliminates the need for separate bonding areas.
Data Source
AI summary
An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.