Backside Channel Plug Layout for Variable Channel Count Stacks
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling transistor dimensions to conserve power and optimize performance, particularly due to edge capacitance and lithography constraints.
Innovation Solution
The semiconductor structure incorporates stacks of semiconducting layers with different numbers of channels, enabled by a method that includes forming backside channel plugs and selectively removing channel regions to optimize power performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If transistor dimensions are reduced to conserve power and optimize performance, then power performance is improved, but edge capacitance and lithography constraints worsen
Solution Approach 1:
The invention divides the semiconductor structure into multiple independent stacks, where each stack contains a selective number of channel layers (e.g., 2, 4, or 6 channels). This segmentation allows different regions to have different channel counts optimized for their specific functions, enabling power performance optimization without being constrained by uniform scaling limitations that exacerbate edge capacitance effects.
Solution Approach 2:
The invention transitions from planar transistor scaling to vertical stacking in the third dimension. By forming multiple stacked channels vertically rather than scaling horizontally, the design achieves higher effective channel width without proportionally increasing edge capacitance, as the gate can surround the channels in three dimensions (gate-all-around structure), improving control and reducing parasitic effects.
2Area of moving object
If advanced scaling technologies are used to reduce transistor dimensions, then device footprint is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The invention segments the channel layers into discrete stacks with different channel counts (2, 4, or 6 channels per stack) that can be selectively formed using standard epitaxial growth and etching processes. This approach achieves footprint reduction through vertical integration without requiring cutting-edge lithography scaling, as the stack formation uses conventional manufacturing techniques applied in a modular fashion.
Solution Approach 2:
The invention performs preliminary formation of all channel layers through epitaxial growth before any selective removal. The sacrificial placeholder layers are pre-formed during the epitaxial process, and then selective etching removes placeholders to create the desired stack configurations. This preliminary action simplifies manufacturing by establishing all structural elements early using standard processes, avoiding the need for complex subsequent scaling operations.
3Ease of manufacture
If uniform channel stacks are used across the device, then manufacturing is simplified, but power performance optimization is limited
Solution Approach 1:
The invention applies local quality by allowing different stacks to have different channel counts (2, 4, or 6 channels) based on their specific functional requirements. Each stack can be optimized locally for its power performance needs while using the same fundamental manufacturing processes. The selective removal of sacrificial placeholder layers enables local differentiation without requiring entirely separate manufacturing flows for each stack type.
Solution Approach 2:
The invention segments the device into multiple independent stacks that can be independently configured with different channel counts. This segmentation allows power performance optimization at the stack level while maintaining manufacturing simplicity through standardized processes applied uniformly across all stacks. The modular stack design enables flexible configuration to meet diverse power performance requirements within the same device.
Data Source
AI summary
A semiconductor structure including a first stack of semiconducting layers, a second stack of semiconducting layers, wherein the first stack of semiconducting layers has at least one fewer layer than the second stack of semiconducting layers, and a backside channel plug directly beneath the first stack of semiconducting layers.