Backside Clock Routing With Feed-Through Vias for Lower IC Delay
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the resistance of conductive lines affects operating voltages and overall IC performance, particularly in memory macros, leading to issues with clock tree resistance and capacitance.
Innovation Solution
The integration of a feed-through via (FTV) that electrically couples elements on the front-side and back-side of a substrate, reducing resistance and capacitance in the clock tree by using backside routing, thereby improving clock cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional front-side routing is used for clock tree, then layout simplicity is maintained, but resistance and capacitance increase leading to performance degradation
Solution Approach 1:
The patent utilizes the backside of the substrate as an additional routing dimension, allowing clock signals to be routed through feed-through vias from the front side to the back side. This three-dimensional routing approach reduces the path length and resistance while distributing capacitance more effectively, thereby improving clock tree performance without being constrained by traditional planar routing limitations.
Solution Approach 2:
The clock tree routing is segmented into multiple paths using feed-through vias that connect front-side clock buffers to back-side routing networks. This segmentation allows the clock signal to be distributed through parallel pathways, reducing the overall resistance and capacitance impact on any single path, and improving timing balance across the memory macro.
2Productivity
If IC size is reduced to increase integration density, then productivity improves, but conductive line resistance increases affecting operating voltages
Solution Approach 1:
By moving clock tree routing to the backside of the substrate and using feed-through vias for vertical connections, the patent creates additional routing resources that reduce the burden on front-side conductive lines. This enables tighter integration and higher density while maintaining lower resistance paths for clock signals, thereby preserving operating voltage stability even as device size decreases.
3Loss of time
If clock tree resistance is reduced through shorter paths, then clock cell delay decreases, but routing complexity and area usage increase
Solution Approach 1:
The patent exploits the vertical dimension by implementing feed-through vias that connect front-side clock buffers to back-side routing networks. This allows clock signals to travel shorter effective paths through the via connections, reducing clock cell delay. The backside routing space is utilized efficiently to distribute clock signals without significantly increasing the planar area footprint, as the routing occurs in the third dimension rather than expanding the two-dimensional layout.
Data Source
AI summary
An integrated circuit includes a first cell region including a first set of transistors of a clock circuit, and a second cell region adjacent to the first cell region along a first boundary. The second cell region includes a feed-through via extending from a front-side to a back-side of a substrate, and being configured to electrically couple elements on the front-side and the back-side together. The feed-through via includes a first conductor on the back-side of the substrate, a second conductor being on a first level and being above the first conductor, a first contact being on a second level, and being above the first conductor, and a first via being on a third level, and being above the first conductor.