Backside Contact Structure for 3D Channel Semiconductor Scaling
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multi-functional semiconductor devices has led to challenges in overcoming limitations due to reduced size and planar metal oxide semiconductor FETs, necessitating the development of semiconductor devices with improved electrical properties and three-dimensional channel structures.
Innovation Solution
A semiconductor device design featuring a substrate insulating layer with a fin structure, semiconductor pattern, channel layers, gate structure, source/drain regions, and a backside contact structure comprising a metal-semiconductor compound layer, insulating liner layers, and conductive layer, which enhances electrical connectivity and resistance properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of planar metal oxide semiconductor FET is reduced to increase integration degree, then device density is improved, but electrical properties deteriorate
Solution Approach 1:
The patent transitions from planar FET to three-dimensional channel structure (FinFET), changing the channel geometry from two-dimensional to three-dimensional. This dimensional change allows continued scaling while maintaining effective gate control and electrical performance through the vertical fin structure that provides superior electrostatic control compared to planar devices.
Solution Approach 2:
The channel is segmented into multiple channel layers stacked vertically, with each layer providing independent current path. This segmentation into multiple thin layers maintains electrical properties by ensuring each layer remains thin enough for effective gate control while collectively providing the required current capacity for the device.
2Reliability
If three-dimensional channel structure is implemented to improve electrical properties, then device performance is improved, but device complexity increases
Solution Approach 1:
The gate structure is designed to surround the channel layers on multiple sides (gate-all-around configuration), providing both vertical and lateral electrostatic control. This multi-functional gate structure simultaneously achieves superior electrical control and can be integrated with standard CMOS fabrication processes, managing complexity through design universality.
Solution Approach 2:
The channel layers are nested within the gate structure, with the gate completely surrounding the channel regions. This nested configuration maximizes gate control efficiency while maintaining a compact footprint, reducing the overall device area and associated interconnect complexity despite the three-dimensional channel structure.
3Power
If backside contact structure is added to enhance electrical connectivity, then power delivery is improved, but manufacturing complexity increases
Solution Approach 1:
The backside contact structure is formed during the fabrication process before final device assembly, with contact regions, vertical regions, and intermediate insulating patterns prepared in advance. This preliminary formation of power delivery paths enables efficient electrical connectivity while integrating the complex structure into the standard fabrication flow, reducing overall manufacturing complexity.
Solution Approach 2:
An intermediate insulating pattern is introduced between the substrate insulating layer and the backside contact structure. This intermediary layer provides electrical isolation and structural support, enabling the complex backside contact architecture to be manufactured using standard deposition and etching processes while achieving superior power delivery performance.
Data Source
AI summary
A semiconductor device may include a substrate insulating layer, a semiconductor pattern extending on the lower insulating pattern, a plurality of channel layers stacked on the semiconductor pattern, a gate structure surrounding the plurality of channel layers, a source/drain region on the semiconductor pattern and opposite sides of the gate structure, a backside contact structure including a contact region connected to the source/drain region, and an intermediate insulating pattern in contact with the semiconductor pattern. The backside contact structure may include a metal-semiconductor compound layer, a first insulating liner layer, a second insulating liner layer, and a conductive layer. The backside contact structure may pass through each of the substrate insulating layer, and the semiconductor pattern. The conductive layer may have a step portion between a first vertical region and a second vertical region of the backside contact structure.