Backside Contact Structures for Low-Capacitance Chip Interconnects
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Solution Overview
Problem
The challenge in the semiconductor industry is to integrate high-performance and low-capacitance, low-power devices into a single chip, while optimizing performance and reducing power consumption.
Innovation Solution
The solution involves forming backside contact structures on semiconductor devices, which include epitaxial deposition, implantation, and drive-in processes to create electrical connections from the backside of the device, allowing for flexible connection types and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional front-side contact structures are used, then device performance can be optimized, but device complexity and power consumption increase
Solution Approach 1:
The patent applies backside contact structures where electrical contacts are formed on the rear surface of the semiconductor device rather than the front surface. This inversion of the conventional contact approach reduces device complexity by separating contact formation from the active device region, while maintaining optimal electrical performance through direct substrate contact.
Solution Approach 2:
The patent transitions from planar front-side contacts to three-dimensional backside contacts by etching through the substrate and forming contacts on the opposite surface. This dimensional change allows contacts to be positioned below the active device region, reducing routing complexity and improving performance.
2Productivity
If more devices are integrated on a single chip, then capacity increases, but power consumption and capacitance increase
Solution Approach 1:
The patent segments the contact formation process by creating separate backside contact regions for different device types (high-performance and low-power devices). This segmentation allows independent optimization of power delivery for each device category, enabling high capacity integration while managing overall power consumption through targeted power distribution.
3Reliability
If backside contact structures are formed, then device performance enhances and power consumption reduces, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates backside contact formation as an early step in the fabrication process, performing substrate thinning and contact hole etching before completing the front-side device processing. This preliminary action integrates backside contacts into the existing manufacturing flow without requiring separate complex processing steps, thereby reducing overall manufacturing complexity despite the added functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of efficient backside interconnects, enhancing device performance and reducing power consumption, while allowing for the integration of both high-performance and low-power devices on a single chip.
Implementation Method 1
epitaxial deposition, implantation, and drive-in processes
Implementation Method 2
epitaxial deposition, implantation, and drive-in processes
Implementation Method 3
epitaxial deposition, implantation, and drive-in processes
Data Source
AI summary
An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.