Backside Source/Drain Contact Layout for Precise GAA Transistors
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Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) manufacturing lies in creating smaller and more complex circuits while maintaining efficient production and reducing costs, particularly in forming gate-all-around (GAA) transistor structures with precise pitch and alignment.
Innovation Solution
The fabrication process involves double-patterning or multi-patterning techniques using photolithography and self-aligned processes to create GAA transistors, including the formation of fins, isolation structures, dummy gate structures, and replacement with metal gates, along with selective etching to define nanosheet channels and form high-k/metal gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-patterning photolithography is used, then the fabrication process is simple, but the pitch and alignment precision required for GAA transistors cannot be achieved
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple discrete steps (first pattern formation, spacer deposition, second pattern formation) rather than attempting to achieve the final pattern in a single step. This multi-patterning approach enables the required pitch precision for GAA transistors by breaking down the complex patterning requirement into manageable sequential operations, where each step contributes to the final precise geometry.
Solution Approach 2:
The patent employs preliminary action through the formation of sacrificial mandrel structures and spacer layers before the final transistor gate patterns are created. These preliminary structures serve as templates that guide subsequent etching and material deposition, ensuring that the final GAA transistor structures achieve the required alignment precision. The dummy gate structures formed in advance also prepare the device for later replacement with metal gates, maintaining precision throughout the process.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases and costs decrease, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent utilizes self-aligned processes where previously formed structures automatically serve as alignment references for subsequent steps. The spacers are deposited conformally on mandrels, and the mandrels themselves become the alignment template for the final transistor patterns. This self-alignment mechanism eliminates the need for separate alignment operations, maintaining precision even as geometry sizes scale down to increase functional density and production efficiency.
3Manufacturing precision
If complex multi-patterning processes are used to achieve precise GAA transistor structures, then pitch and alignment precision improve, but fabrication time and process complexity increase
Solution Approach 1:
The patent merges multiple functions into integrated process steps. For example, the spacer deposition step simultaneously serves as both a pattern definition step and a material layer formation step. The dummy gate structure formation combines gate patterning with the creation of sacrificial structures that will later be replaced. This merging of functions reduces the total number of discrete process steps, thereby reducing fabrication time while maintaining the precision benefits of multi-patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of advanced GAA transistors with improved performance and reduced parasitic resistance, enhancing the functional density and efficiency of ICs.
Implementation Method 1
The fabrication process involves double-patterning or multi-patterning techniques using photolithography
Implementation Method 2
double-patterning or multi-patterning techniques using photolithography and self-aligned processes
Data Source
AI summary
An integrated circuit (IC) structure includes a channel region, a gate structure, an isolation structure, a source/drain epitaxial structure, and a backside source/drain contact. The channel region extends along a first direction. The gate structure is over the channel region. The gate structure and the isolation structure extend along a second direction different from the first direction and spaced apart from each other. The source/drain epitaxial structure is between the gate structure and the isolation structure. The backside source/drain contact is on a backside of the source/drain epitaxial structure. A space between the backside source/drain contact and the isolation structure is less than a space between the backside source/drain contact and the first gate structure in a first top view.