Backside Active Contact Layout for Scaled MOSFET Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are scaled down, their operational characteristics deteriorate due to challenges in maintaining electrical performance and efficiency.
Innovation Solution
A semiconductor device design featuring a substrate with a lower power line, source/drain patterns, a channel pattern, a gate electrode, and backside active and isolation structures, where the uppermost surface of the backside active contact is higher than the isolation structure, enhancing electrical connectivity and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the metal-oxide-semiconductor field effect transistor is scaled down to reduce device size, then the device size and design rule are reduced, but the operational characteristics of the semiconductor device deteriorate
Solution Approach 1:
The patent introduces a backside active contact that penetrates through the substrate from the rear surface, adding a vertical dimension to the electrical connection path. This allows source/drain regions to be electrically connected from the backside, enabling continued scaling of the front surface device dimensions without proportionally increasing interconnect complexity, thus maintaining operational characteristics at smaller sizes
Solution Approach 2:
The patent segments the electrical connection path by separating the front surface active regions from the backside contact structure. The backside active contact is divided into multiple portions (first portion in the first source/drain region, second portion in the second source/drain region) that are electrically isolated from each other, allowing independent optimization of each connection path while maintaining overall device functionality at scaled dimensions
Data Source
AI summary
Provided is a semiconductor device including a substrate, a lower power line disposed under the substrate, a source/drain pattern on the substrate, a channel pattern, on side surfaces of the source/drain pattern, including a plurality of semiconductor patterns stacked on each other, a gate electrode between the plurality of semiconductor patterns, a backside active contact penetrating the substrate to electrically connect the lower power line and the source/drain pattern, and a backside isolation structure penetrating the substrate and the backside active contact, and disposed under the gate electrode. An uppermost surface of the backside active contact is located at a higher level than an uppermost surface of the backside isolation structure.