Backside Source-Drain Contact Selectivity for Scaled Nanowire ICs
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to edge placement errors and the need for efficient power delivery as semiconductor dimensions shrink, limiting further miniaturization and increasing manufacturing complexity.
Innovation Solution
The implementation of backside source or drain contact selectivity through a self-aligned coloring flow and hardmask selectivity, allowing for reduced edge placement errors and efficient power delivery by routing power from the wafer backside, eliminating the need for front-side power delivery networks and reducing interconnect complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate transistors are scaled down to smaller dimensions, then device density increases, but edge placement errors increase and manufacturing precision deteriorates
Solution Approach 1:
The patent implements backside contact formation instead of conventional front-side contact formation. By accessing the source/drain regions from the wafer backside through through-silicon vias, the method inverts the traditional contact architecture, enabling precise alignment independent of front-side lithography variations and reducing edge placement errors in scaled devices
Solution Approach 2:
The patent separates contact formation into distinct front-side and backside processing steps. Front-side processing completes the transistor structures, then the wafer is flipped for backside contact formation. This segmentation allows independent optimization of each process, improving overall manufacturing precision despite smaller dimensions
2Use of energy by moving object
If conventional front-side power delivery networks are used, then power can be delivered to devices, but interconnect complexity and cell height increase
Solution Approach 1:
The patent moves power delivery from the conventional two-dimensional front-side plane to the third dimension by routing power contacts from the wafer backside. This vertical transition through through-silicon vias enables power delivery without increasing lateral interconnect complexity or cell height on the front side
Solution Approach 2:
The patent extracts the power delivery function from the front-side interconnect network and implements it separately on the backside. By taking out power contacts from the congested front-side layout and placing them on the backside, the method reduces front-side interconnect complexity while maintaining efficient power delivery
Data Source
AI summary
Integrated circuit structures having backside source or drain contact selectivity are described. In an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.