Backside Source/Drain Contacts for Low-IR-Droop IC Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of integrated circuits to the 10 nanometer node or sub-10 nanometer range, particularly in multi-gate transistors, leading to challenges in optimizing device performance and integrating new technologies.
Innovation Solution
The implementation of front-side-cut backside source or drain contacts, including pixel-assisted backside only pinhole mirror structures and backside patterning of contact plugs, allows for direct power delivery from the wafer backside, simplifying the process flow and reducing process complexity while enabling improved scaling and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing process infrastructure is maintained, but manufacturing precision and device performance optimization are limited at 10nm node and below
Solution Approach 1:
The patent segments the contact formation process into front-side patterning (defining contact locations) and back-side execution (forming actual contacts). This segmentation allows each side to be optimized independently: front-side uses conventional high-precision lithography for positioning, while back-side uses specialized processes for actual contact formation, thereby achieving both manufacturing precision and process adaptability at 10nm node
Solution Approach 2:
The patent transitions from traditional single-sided (front-side only) contact formation to dual-sided (front-side and back-side) contact formation. By utilizing the back-side of the wafer for contact plug formation, the process gains an additional dimensional freedom, enabling new fabrication methodologies that overcome conventional process limitations while maintaining compatibility with existing front-side infrastructure
2Area of moving object
If feature size is reduced to increase device density, then chip capacity increases, but process constraints become overwhelming
Solution Approach 1:
The patent divides the complex contact formation process into separate front-side and back-side operations. The front-side handles pattern definition with simplified processes, while the back-side handles contact formation with specialized processes. This segmentation reduces the complexity burden on any single process step, enabling scaling to smaller features without overwhelming process constraints
Solution Approach 2:
The patent introduces an intermediary approach where the front-side pattern serves as a template or guide, and the back-side process executes the actual contact formation. This intermediary separation allows each side to be optimized for its specific function, reducing overall process complexity while enabling higher device density through precise contact placement
3Device complexity
If power wires and signal wires are integrated on the same side, then routing is simplified, but on-chip IR droop increases
Solution Approach 1:
The patent separates power delivery and signal routing into different spatial dimensions: power delivery is implemented through back-side contact plugs that provide direct vertical access to power regions, while signal routing remains on the front-side interconnect layers. This dimensional separation eliminates the need for power and signal wires to share the same lateral routing space, thereby reducing IR droop while maintaining routing simplicity
Solution Approach 2:
The patent extracts the power delivery function from the conventional front-side interconnect stack and implements it through dedicated back-side contact plugs. By taking out the power delivery path from the signal routing layer, the patent eliminates the harmful interaction between power and signal wires, reducing IR droop while keeping the overall routing architecture simple
Data Source
AI summary
Integrated circuit structures having front-side-cut backside source or drain contacts are described. In an example, an integrated circuit structure includes a first gate stack over a first plurality of horizontally stacked nanowires or fin, and a second gate stack over a second plurality of horizontally stacked nanowires or fin. A first epitaxial source or drain structure is at an end of the first plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a backside contact structure thereon. A second epitaxial source or drain structure is at an end of the second plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is laterally between and in contact with the backside dielectric structure and the backside contact structure.