Backside Source-Drain Contacts for Sub-10 nm Interconnect Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of integrated circuits to the 10 nanometer node or sub-10 nanometer range, necessitating new methodologies for multi-gate transistors, particularly in bulk silicon substrates, to optimize performance and reduce complexity.
Innovation Solution
Implementing front-side-guided backside source or drain contacts with backside power delivery, utilizing differentiated access features and self-aligned processes to simplify fabrication and reduce interconnect congestion, enabling direct power delivery to transistors from the wafer backside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing process infrastructure can be maintained, but manufacturing precision and reliability deteriorate at 10 nanometer node or sub-10 nanometer range
Solution Approach 1:
The patent inverts the conventional approach by forming source and drain contacts from the backside of the substrate rather than from the front side. This backside contact formation enables direct connection to the substrate without requiring complex front-side interconnect structures, thereby improving manufacturing precision and reducing process variability at advanced technology nodes
Solution Approach 2:
The patent transitions from planar front-side contact formation to three-dimensional backside contact formation. By accessing the substrate from the opposite dimension (backside versus front side), the invention enables direct source/drain contact formation that bypasses intermediate interconnect layers, improving fabrication precision at sub-10 nanometer nodes
2Power
If front-side interconnect structures are used for power delivery, then power can be delivered to transistors, but interconnect congestion increases and device complexity increases
Solution Approach 1:
The patent extracts the power delivery function from the congested front-side interconnect network and relocates it to the backside of the substrate. By forming direct source/drain contacts from the backside, power delivery is achieved without requiring additional front-side interconnect layers, thereby reducing interconnect congestion and device complexity
Solution Approach 2:
The patent inverts the power delivery approach by delivering power from the backside of the substrate rather than through front-side interconnect structures. This backside power delivery method eliminates the need for complex front-side power networks, reducing both interconnect congestion and device complexity while maintaining effective power delivery
Data Source
AI summary
Integrated circuit structures having front-side-guided backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.