Backside Dummy Plugs for 3D Integration Thermal and Stress Management

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Solution Overview

Problem

3D integration in semiconductor chip stacking faces limitations due to inter-wafer thermal conductivity, signal cross-talk, and structural reliability issues, particularly mechanical stress caused by mismatched thermal expansion coefficients in through-substrate vias (TSVs), which degrade system performance and can lead to cracking and dislodging of TSVs.

Innovation Solution

Incorporating backside dummy plugs with cavities in the substrate, which can be conductive or insulating, to enhance thermal conductivity, reduce signal cross-talk, and alleviate mechanical stress by accommodating volume changes during thermal cycling, thereby improving the reliability and integrity of TSVs without requiring additional active areas.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a large number of TSVs are formed to enhance inter-wafer thermal conductivity, then thermal conductivity is improved, but chip area available for active areas is reduced

Engineering Contradiction:
Improveinter-wafer thermal conductivityVSAvoidchip area for active areas
Core Design Contradiction:
TemperatureVSArea of stationary object

Solution Approach 1:

The patent introduces dummy plugs that replicate the thermal conduction function of TSVs without requiring full electrical connectivity. These dummy plugs are positioned in non-active areas and provide thermal pathways similar to TSVs, effectively copying the thermal management benefit while preserving active chip area for functional devices.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent applies different structures to different regions of the chip: functional TSVs are placed in active areas where electrical connectivity is needed, while dummy plugs are placed in non-active areas where only thermal conduction is required. This local differentiation optimizes both thermal management and active area utilization.

Inventive Principle:
Principle #3Local quality

2Reliability

If shielding structures are formed to reduce signal cross-talk between TSVs, then signal integrity is improved, but active area is reduced

Engineering Contradiction:
Improvesignal integrityVSAvoidactive area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the shielding function from the TSV structure itself and implements it separately through dummy plugs. The dummy plugs are positioned to provide electromagnetic shielding for nearby TSVs without requiring the TSVs themselves to be modified with shielding structures, thereby reducing active area consumption while maintaining signal integrity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of energy

If the number of TSVs is increased to provide sufficient cooling, then thermal management is improved, but overall chip size or active area is reduced

Engineering Contradiction:
Improveheat dissipationVSAvoidactive area for semiconductor devices
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The dummy plugs replicate the thermal conduction pathway of full TSVs but are positioned in non-active areas. They provide alternative heat dissipation routes that do not consume active chip area, effectively copying the thermal management function while preserving device fabrication space.

Inventive Principle:
Principle #26Copying

4Reliability

If backside dummy plugs with cavities are formed to accommodate volume changes, then mechanical stress is reduced, but device complexity increases

Engineering Contradiction:
Improvestructural reliabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy plugs serve multiple functions simultaneously: they provide thermal conduction pathways, electromagnetic shielding, and mechanical stress relief through their cavity structures. This multi-functionality reduces the need for separate structures for each purpose, thereby managing complexity while delivering multiple benefits.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The backside dummy plugs enhance vertical thermal conductivity, decouple electrical signals, and reduce mechanical stress, improving the reliability and signal integrity of TSVs, thus addressing the limitations of 3D integration without increasing chip size or active area usage.

Implementation Method 1

The backside dummy plugs can be a conductive structure that enhances vertical thermal conductivity of the semiconductor structure

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

The backside dummy plug can include a cavity to accommodate volume changes in other components in the substrate, thereby alleviating mechanical stress in the substrate during thermal cycling

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS8587121B2Backside dummy plugs for 3D integration
Publication Date: 2013.11.19 GLOBALFOUNDRIES US INC
  • US8587121B2 patent drawing
  • US8587121B2 patent drawing
  • US8587121B2 patent drawing

AI summary

A semiconductor structure includes backside dummy plugs embedded in a substrate. The backside dummy plugs can be a conductive structure that enhances vertical thermal conductivity of the semiconductor structure and provides electrical decoupling of signals in through-substrate vias (TSVs) in the substrate. The backside dummy plug can include a cavity to accommodate volume changes in other components in the substrate, thereby alleviating mechanical stress in the substrate during thermal cycling and operation of the semiconductor chip. The backside dummy plug including the cavity can be composed of an insulator material or a conductive material. The inventive structures can be employed to form three-dimensional structures having vertical chip integration, in which inter-wafer thermal conductivity is enhanced, cross-talk between signals through TSVs is reduced, and/or mechanical stress to the TSVs is reduced.