At-Speed IC Testing via Backside Electrical Probing
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Solution Overview
Problem
Current techniques for at-speed integrated circuit testing, such as light-induced voltage alteration and dynamic laser probing, are inadequate for high-speed wafer-level and in-circuit logic analysis due to slow detection rates and wasteful scanning methods, failing to effectively identify and locate dynamic logic states and timing information across modern ICs.
Innovation Solution
The implementation of a system with electrical and optical detection circuitry that receives and analyzes radiation reflected or emitted from ICs, using high-speed digitizers and customized signal processing to extract logic states and timing information, allowing for focused probing of specific areas of interest and real-time comparison with reference patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If light-based techniques (LIVA or Photon Emission Mapping) are used to read perturbations through the substrate, then access to internal areas is achieved, but detection speed is far slower than IC clock rates
Solution Approach 1:
The patent replaces light-based detection with electrical field-based detection using scanning probe microscopy. Instead of using photons to detect internal states, the system uses electrical probes to directly sense voltage and current perturbations, enabling detection speeds that match modern IC clock rates while maintaining access to internal areas through the substrate
Solution Approach 2:
The patent changes the detection parameter from optical (light absorption/emission) to electrical (voltage/current measurement). This parameter change allows the system to achieve both substrate access and high-speed detection by measuring electrical signals that change rapidly with logic state transitions
2Reliability
If legacy probing techniques are used with metallic probes to frontside metal lines, then electrical contact is established, but the technique becomes increasingly problematic as metal line layers increase
Solution Approach 1:
The patent inverts the probing approach by accessing the IC through the backside substrate rather than through the frontside metal lines. This inversion allows electrical contact to be established at the substrate level, bypassing the complexity of multiple metal line layers while maintaining reliable electrical contact for probing internal nodes
3Measurement precision
If dynamic laser probing is used to detect perturbations, then logic state detection is achieved, but scanning time is excessive and processing is not real-time
Solution Approach 1:
The patent extracts only the necessary measurement points for logic state detection using targeted electrical probing, rather than performing comprehensive optical scanning. By selectively measuring voltage and current at specific probe locations, the system achieves precise logic state detection without the time-consuming overhead of full-field optical scanning
Solution Approach 2:
The patent implements continuous real-time measurement of electrical signals at probe locations, allowing logic state detection to occur continuously as the IC operates. This eliminates the sequential scanning approach where measurement must wait for complete scanning cycles, enabling detection speeds that keep pace with IC clock rates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables fast and efficient at-speed integrated circuit device observation and analysis, reducing unnecessary scanning and processing time, and achieving real-time or near-real-time detection of logic states and patterns, thereby overcoming the limitations of legacy methods.
Implementation Method 1
receives and analyzes radiation reflected or emitted from ICs
Data Source
AI summary
A method, system, and computer program product for integrated circuit wafer and die testing. The method commences by selecting areas of interest accessible from a backside of an integrated circuit where the areas of interest correspond to electronic devices (e.g., gates or transistors or vias or pads). Then, using a small-beam light source such as a laser, illuminating the areas of interest and collecting the reflected signal returned from illuminated areas of interest. A processor analyses the reflected signal to determine logic states and timing information of the electronic devices and compares the determined logic states and timing information to a pre-determined logic pattern to identify one or more errors as observed from the actual electronic devices. Specific points within an area of interest are determined from CAD layout data, and the pre-determined logic patterns can be retrieved from CAD simulation data.