Backside Conductive Feed-Throughs for Low-Resistance IC Power Delivery
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Solution Overview
Problem
The variability in conventional fabrication processes limits the possibility to further extend integrated circuits into the 10 nanometer node or sub-10 nanometer range, and there is a need for new methodologies to optimize performance and reduce constraints on semiconductor processes, especially for multi-gate transistors like tri-gate transistors.
Innovation Solution
The integration of backside conductive feed-throughs and differentiated backside access features in integrated circuit structures, including self-aligned low resistance contacts and backside power delivery, which are compatible with existing library cell design conventions and transistor contact process flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing process infrastructure can be maintained, but manufacturing precision and reliability deteriorate at 10 nanometer node and below
Solution Approach 1:
The patent introduces backside access features that extend the fabrication dimension from the traditional front-side-only approach to include the substrate backside. This dimensional change enables new process methodologies for forming conductive feed-throughs and power delivery structures, allowing precise control of electrical properties without being constrained by front-side process variability at 10nm node and below
2Loss of energy
If front-side power delivery is used, then power can be delivered to transistors, but power network resistance increases and standard cell height must be increased
Solution Approach 1:
The patent inverts the traditional power delivery approach by delivering power from the backside of the substrate rather than from the front side. This inversion creates backside conductive feed-throughs that directly connect to transistor power terminals, significantly reducing power network resistance and eliminating the need to increase standard cell height for power delivery
3Quantity of substance
If multi-gate transistors are scaled down, then device density increases, but process constraints become overwhelming
Solution Approach 1:
The patent segments the transistor contact and power delivery formation into distinct front-side and back-side process sequences. The backside access features are formed independently on the substrate backside, allowing parallel processing and reducing the overall process constraint complexity while enabling higher device density through multi-gate transistor scaling
Data Source
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AI summary
Integrated circuit structures having backside conductive feed-throughs are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires or fin laterally spaced apart from a second plurality of horizontally stacked nanowires or fin. A first gate stack is over the first plurality of horizontally stacked nanowires or fin, and a second gate stack is over the second plurality of horizontally stacked nanowires or fin. An epitaxial source or drain structure is on a front side conductive contact between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin. A backside conductive structure extends entirely through the epitaxial source or drain structure to the front side conductive contact.