Backside Fin Isolation Structure Using Air Gaps Between Transistors
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Solution Overview
Problem
The challenge in semiconductor technology is to prevent the merging of source, drain, and gate regions in closely spaced transistor devices, which can lead to electrical isolation issues and render transistors inoperable, especially when insulator materials are used between fins during front-end processing, due to thermal budget constraints and high stress levels.
Innovation Solution
The method involves back-side processing where the integrated circuit structure is flipped, and isolation material between semiconductor fins is recessed to expose sub-channel portions, followed by the deposition of spacers around the fins to protect them during further etching, forming air gaps between adjacent transistor devices, which can be filled with low-k dielectric materials for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If insulator materials are used between fins during front-end processing, then electrical isolation between adjacent transistor devices is achieved, but thermal budget constraints and high stress levels cause merging of source, drain, and gate regions
Solution Approach 1:
The patent applies segmentation by dividing the isolation function into two distinct stages: first, insulator materials are deposited between fins during front-end processing to provide initial electrical isolation; second, air gaps are formed between adjacent transistor devices through back-end recessing processes. This segmentation allows each isolation mechanism to operate optimally without interfering with the other, resolving the contradiction between maintaining electrical isolation and preventing region merging under thermal and stress constraints.
Solution Approach 2:
The patent implements preliminary action by depositing insulator materials between fins during front-end processing before the merging issue becomes critical. This preliminary isolation structure is then preserved through the manufacturing process, and air gaps are subsequently formed in the back-end to prevent merging. The preliminary insulator deposition establishes a foundation for electrical isolation that works in conjunction with the later air gap formation to maintain both isolation and region separation.
2Productivity
If fins are placed closely spaced to increase device density, then productivity is improved, but source, drain, and gate regions merge leading to inoperable transistors
Solution Approach 1:
The patent applies dimensionality change by transitioning from two-dimensional planar isolation to three-dimensional air gap formation. Air gaps are recessed from both the front surface and back surface of the substrate, creating vertical separation between adjacent transistor devices. This 3D approach allows fins to be placed closer together horizontally (increasing density) while maintaining vertical isolation that prevents merging of source, drain, and gate regions, thus resolving the contradiction between device density and transistor functionality.
Solution Approach 2:
The patent segments the air gap formation process into multiple steps: first recessing isolation material from the front surface to expose fin tops, then depositing spacers, and finally recessing from the back surface to complete the air gaps. This segmentation enables precise control over gap dimensions and positioning, allowing close fin spacing for high density while ensuring adequate separation to maintain transistor functionality.
3Manufacturing precision
If air gaps are formed between adjacent transistor devices to prevent merging, then region separation is achieved, but additional processing steps increase manufacturing complexity
Solution Approach 1:
The patent implements universality by designing the air gap formation process to serve multiple functions simultaneously: the same recessing and spacer deposition steps that create air gaps also define fin heights, establish alignment references for subsequent processing, and create isolation structures. This multi-functionality reduces the need for separate dedicated steps, thereby limiting the increase in manufacturing complexity while achieving precise region separation.
Solution Approach 2:
The spacer structures deposited during air gap formation serve dual purposes: they act as etch stop layers that define the depth of recessing, and they become part of the final transistor structure as sidewall spacers. This self-service approach allows the process to self-regulate gap dimensions without requiring additional measurement or control steps, reducing manufacturing complexity while maintaining precise region separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates the merging of transistor regions, ensuring electrical isolation and allowing for the placement of closely spaced fins without requiring isolation structures during front-end processing, thereby improving the operational integrity of semiconductor devices.
Implementation Method 1
a spacer is formed around a full perimeter of the exposed sub-channel portion of each fin
Data Source
AI summary
Techniques are disclosed for forming integrated circuit structures having a plurality of non-planar transistors. An insulation structure is provided between channel, source, and drain regions of neighboring fins. The insulation structure is formed during back side processing, wherein at least a first portion of the isolation material between adjacent fins is recessed to expose a sub-channel portion of the semiconductor fins. A spacer material is then deposited at least on the exposed opposing sidewalls of the exposed sub-channel portion of each fin. The isolation material is then further recessed to form an air gap between gate, source, and drain regions of neighboring fins. The air gap electrically isolates the source/drain regions of one fin from the source/drain regions of an adjacent fin, and likewise isolates the gate region of the one fin from the gate region of the adjacent fin. The air gap can be filled with a dielectric material.