Backside Floating Node Circuit for Low-Voltage Boosting
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Solution Overview
Problem
Existing integrated circuits face challenges in achieving low voltage functionality due to BEOL congestion and limited voltage boost from virtual nodes, primarily due to capacitance between the virtual node and transient line.
Innovation Solution
The implementation of a floating node structure in integrated circuits, utilizing a pre-charging or pre-discharging circuit with a virtual power rail capacitively coupled to a transient line, and interdigitated conductive teeth separated by a dielectric, to achieve voltage differentials and enhance coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a virtual node is formed on the front side of the wafer using continued buildup on the back end of the line with multiple wiring layers, then voltage boosting functionality is achieved, but BEOL congestion is increased
Solution Approach 1:
The patent moves the virtual node formation from the front side to the back side of the wafer, utilizing the back end of line (BEOL) wiring layers. This dimensional transition allows the virtual node to be formed in the less congested back side region while maintaining the voltage boosting functionality, thereby resolving the contradiction between achieving voltage boost and avoiding BEOL congestion
2Power
If the virtual node is capacitively coupled to the transient line, then voltage boosting is achieved, but the boost is limited by the capacitance between the virtual node and transient line
Solution Approach 1:
The patent implements a pre-charging circuit that charges the virtual node to a predetermined voltage level before the main operation. This preliminary action prepares the virtual node in advance, allowing it to achieve the required voltage boost magnitude without being constrained by the capacitive coupling limitations during the actual operation phase
3Reliability
If separate voltage supplies are used for logic and memory circuits, then proper voltage levels are maintained, but device density is reduced
Solution Approach 1:
The patent creates a universal voltage supply mechanism where the back end of line wiring layers serve multiple functions: they provide both the standard power distribution and the virtual node formation for voltage boosting. This multi-functionality eliminates the need for separate voltage supplies while maintaining proper voltage levels, thereby increasing device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for low-voltage functionality in logic and memory circuits, reducing the need for separate voltage supplies, increasing density, and providing positive or negative voltage boosts to bit lines in memory arrays.
Implementation Method 1
a transient line capacitively but not conductively coupled to the virtual power rail
Implementation Method 2
the virtual power rail and the transient line are formed with interdigitated conductive teeth separated by a dielectric
Data Source
AI summary
A semiconductor structure includes a device layer including a device region with a plurality of devices and a pre-charging circuit; a front side wiring layer, located on a front side of the device layer, and including at least signal wiring connected to the device region; a supply voltage line coupled to the device region; and a back side wiring layer, located on a back side of the device layer. The back side wiring layer includes a virtual power rail coupled to the pre-charging circuit and a transient line capacitively but not conductively coupled to the virtual power rail and coupled to the device region. The pre-charging circuit is configured to cause the virtual power rail to experience a voltage differential from a supply voltage applied to the supply voltage line responsive to a pulse on the transient line.