Backside GAA Source/Drain Structure for Wider TDDB Isolation
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in addressing the short problem between backside source/drain via and gate structure, which affects the reliability and performance of semiconductor devices, particularly in advanced gate all around (GAA) transistor structures.
Innovation Solution
The implementation of a deep source/drain epitaxial structure and a selective-growth dielectric layer at the backside of the semiconductor device to create a larger time-dependent dielectric breakdown (TDDB) window between the gate structure and backside interconnection structure, utilizing epitaxial processes to enhance carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional source/drain structure is used, then the manufacturing process is simpler, but the TDDB window between gate structure and backside interconnection structure is reduced
Solution Approach 1:
The patent transitions from a planar source/drain structure to a deep three-dimensional epitaxial structure that extends vertically beneath the gate structure. This dimensional change creates additional separation distance in the vertical dimension, thereby increasing the TDDB window and improving reliability without occupying lateral space that would increase device complexity.
Solution Approach 2:
The deep source/drain epitaxial structure is nested beneath the gate structure, with the source/drain region extending downward into the substrate below the gate. This nesting arrangement allows the source/drain structure to provide both electrical function and isolation function simultaneously, increasing the TDDB window while maintaining compact device geometry.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases and costs decrease, but the short problem between backside source/drain via and gate structure worsens
Solution Approach 1:
As device dimensions are scaled down in the lateral plane to increase functional density, the patent compensates by extending the source/drain structure in the vertical dimension. This allows the TDDB window to be maintained or increased even as lateral dimensions decrease, enabling continued scaling while preserving reliability.
Solution Approach 2:
The patent changes the depth parameter of the source/drain epitaxial structure to compensate for reductions in lateral dimensions. By increasing the vertical extent of the source/drain region, the TDDB window is maintained despite scaling down the overall device geometry, allowing continued productivity improvement through scaling.
3Reliability
If a deep source/drain epitaxial structure is implemented, then the TDDB window is increased and reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The deep source/drain epitaxial structure is formed preliminarily during the epitaxial growth stage, before subsequent processing steps. By establishing the deep structure early in the manufacturing sequence, the need for complex post-processing steps to create the deep profile is eliminated, reducing overall manufacturing complexity despite the advanced structure.
Solution Approach 2:
The epitaxial growth process self-organizes to create the deep source/drain structure with appropriate doping profiles and material composition gradients. The in-situ doping during epitaxial growth automatically provides the required doping distribution without requiring separate ion implantation and annealing steps, simplifying the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and performance of semiconductor devices by enhancing the TDDB window and reducing the risk of electrical breakdown, thereby improving the overall functionality and efficiency of the semiconductor devices.
Implementation Method 1
utilizing epitaxial processes to enhance carrier mobility and device performance
Data Source
AI summary
A device includes a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a front-side interconnection structure, and a backside via. The gate structure is across the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the gate structure and are connected to the channel layer. A height of the first source/drain epitaxial structure and a width of the first source/drain epitaxial structure are different. The front-side interconnection structure is on a front-side of the first source/drain epitaxial structure. The backside via is connected to a backside of the first source/drain epitaxial structure. A backside surface of the first source/drain epitaxial structure is at a level between a level of a backside surface of the backside via and a level of a backside surface of the gate structure.