Backside Gate Cut Replacement Material for Gate Damage Mitigation

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Solution Overview

Problem

Conventional methods for forming gate cut features in semiconductor fabrication are inefficient and can cause damage to the gate structure, leading to performance degradation in field-effect transistors as device sizes decrease.

Innovation Solution

The formation of gate cut features is performed from the backside of the substrate, involving the deposition of a sacrificial material within the trench, followed by filling it with a dielectric material and then replacing it with a work-function metal to repair any damage caused during the etching process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional methods are used to form gate cut features, then the gate structure can be isolated, but damage is caused to the gate structure leading to performance degradation

Engineering Contradiction:
Improvegate structure integrityVSAvoiddamage to gate structure
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent performs the gate cut isolation from the backside of the substrate rather than the front side. This inversion of the processing approach allows the gate cut feature to be formed without directly exposing and damaging the gate structure, as the etching process approaches from the opposite direction through the substrate.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces a replacement material that serves as an intermediary substance to fill the gate cut feature. This replacement material acts as a mediator that protects the gate structure from direct exposure to etchants and processing conditions that would cause damage, while still achieving the desired electrical isolation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If device size is decreased to increase functional density, then production efficiency increases, but device performance degradation occurs

Engineering Contradiction:
Improvefunctional densityVSAvoiddevice performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from front-side processing to backside processing, adding a dimensional aspect to the gate cut formation process. This dimensional change allows for better control of the isolation process at scaled dimensions, preventing performance degradation while maintaining high functional density through continued miniaturization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If gate cut feature is formed to isolate gate structure, then short-channel effects are reduced, but damage to gate structure occurs during etching

Engineering Contradiction:
Improvegate controlVSAvoiddamage during etching process
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

By inverting the processing approach and forming the gate cut from the backside, the patent eliminates direct exposure of the gate structure to damaging etchants during the isolation process, while still achieving the necessary electrical separation to control short-channel effects.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent converts the potentially harmful etching process into a beneficial isolation mechanism by performing it from the backside. The same etching process that would normally damage the gate structure is instead used to create clean isolation regions without direct contact with the gate, turning a harmful process into a beneficial one.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS12519009B2Replacement material for backside gate cut feature
Publication Date: 2026.01.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12519009B2 patent drawing
  • US12519009B2 patent drawing
  • US12519009B2 patent drawing

AI summary

A semiconductor structure includes a substrate, a first gate structure and a second gate structure disposed over the substrate, and an isolation feature extending through the substrate and disposed between the first gate structure and the second gate structure. A top surface of the isolation feature is above a topmost surface of the first gate structure.