Backside Gate Contact Layout for Dense Nanosheet Interconnects
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller nodes, the challenge of densely packing devices requires efficient interconnect structures with reduced conductive features on one side of the substrate, which existing contact structures fail to adequately address, impacting device performance due to the close proximity of adjacent conductive features.
Innovation Solution
The introduction of backside contacts to gate structures and source/drain features, allowing for in-cell routing and reducing the number of metal lines on the front side of the substrate, is achieved through a method involving the formation of backside gate and source/drain contacts that are electrically coupled, with conductive features connecting them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing contact structures are used, then device fabrication can proceed with conventional interconnect routing, but the number of metal lines on the front side increases and device density is limited
Solution Approach 1:
The patent introduces backside contacts that extend through the substrate thickness dimension, allowing gate and source/drain connections to be established from the rear surface. This vertical dimension utilization reduces the horizontal routing burden on frontside metal layers, enabling higher device density without proportionally increasing frontside interconnect complexity
Solution Approach 2:
The patent divides the interconnect function into separate segments: frontside contacts handle local source/drain connections, while backside contacts handle gate connections. This segmentation allows independent optimization of frontside signaling and backside gating, reducing the need for extensive frontside metal routing and improving device packing density
2Device complexity
If backside contacts are introduced, then the number of frontside metal lines is reduced, but additional processing steps and structural complexity are required
Solution Approach 1:
The patent forms backside contacts at an early stage in the fabrication sequence, before frontside interconnect layers are deposited. The backside gate contacts are established through the substrate, and isolation structures are formed around them in advance, preparing the structure for subsequent frontside processing without requiring complex late-stage modifications
Solution Approach 2:
The patent introduces isolation structures (such as dielectric materials or etch stop layers) as intermediary elements between the backside contacts and the frontside active regions. These intermediaries facilitate selective processing, allowing frontside metallization to be deposited and patterned without inadvertently modifying or shorting the backside contact structures
3Productivity
If conductive features are placed in close proximity for high density, then device packing increases, but leakage current between adjacent features increases
Solution Approach 1:
The patent introduces isolation structures (dielectric materials, oxide layers, or etch stop layers) as intermediary barriers between adjacent backside gate contacts and source/drain regions. These intermediaries electrically isolate closely spaced conductive features, preventing leakage current while allowing high device packing density to be achieved
Solution Approach 2:
The patent applies different material properties to different regions: highly conductive materials for contact regions, and highly resistive dielectric materials for isolation regions. This local differentiation of electrical properties enables close spacing of active devices while maintaining electrical isolation through strategically placed high-resistivity barriers
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.