Backside Gate Connection Layout for Scaled Nanowire Transistors
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, and existing power delivery methods occupy valuable space, increasing signal routing tracks and resistance.
Innovation Solution
The implementation of backside gate-to-contact connections and power delivery, where a pre-patterned gate-to-contact connection is formed on the substrate before ribbon/poly patterning, enabling epitaxial growth and direct short between drain and gate, and power is delivered from the wafer backside, reducing space requirements and interconnect stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing compatibility is maintained, but manufacturing precision deteriorates at 10 nanometer node and below
Solution Approach 1:
The patent applies backside gate connection, inverting the conventional front-side gate connection approach. By forming the gate connection on the backside of the substrate, the patent achieves improved manufacturing precision at sub-10 nanometer nodes while maintaining compatibility with conventional bulk silicon fabrication processes. This inversion allows for better control of critical dimensions and reduced process variability.
2Area of stationary object
If power delivery is performed through front-side interconnect tracks, then power delivery function is achieved, but area occupied increases and signal routing resistance increases
Solution Approach 1:
The patent moves the power delivery function from the front-side two-dimensional plane to the backside of the substrate, utilizing the third dimension (depth). By forming power delivery connections on the backside, the patent reduces the area occupied on the front-side interconnect tracks and minimizes signal routing resistance, as power and signal tracks can be separated in the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances scaling capability, reduces electrical resistance, and improves performance by minimizing cell height and signal routing tracks, allowing for more aggressive diffusion and layout density, while maintaining compatibility with existing infrastructure.
Implementation Method 1
enabling epitaxial growth and direct short between drain and gate
Data Source
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AI summary
Integrated circuit structures having backside gate connection are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive gate-to-contact connection is vertically beneath the epitaxial source or drain structure and vertically beneath and in electrical contact with the gate stack.