Nanoinformatics TRIZ Cases

A two-layer tapered inner spacer in nanosheet GAAFETs prevents dielectric pinch-off and lowers parasitic capacitance at scaled nodes.

Low-temperature Si/SiGe deposition creates abrupt diffusion interfaces for selective etching and uniform horizontal nanowires in GAA transistors.

A self-aligned oxidized SiGe mask simplifies GAA transistor fabrication, reducing alignment risk, process complexity, and yield loss.

A layered source/drain doping profile limits dopant out-diffusion, reducing short channel effect while lowering contact resistance in FETs.

Dielectric dummy fins shift gate cut placement away from tight fin spacing, easing overlay limits while enabling denser FinFET and GAA layouts.

An MFMIS ferroelectric transistor improves dense memory integration by reducing charge trapping through capacitance and layer-dimension tuning.

An ONNO charge-trapping stack with oxygen-rich and oxygen-lean nitride layers cuts leakage, improves retention, and fits CMOS logic flows.

Backside gate-to-contact routing frees front-side tracks in scaled nanowire transistors, cutting resistance and cell height.

Sealed self-aligned air spacers cut total capacitance while preserving FinFET gate uniformity, improving parametric consistency and yield.

A buried low-k dielectric and nitride cap improve etch control at source-drain to gate connections, reducing open circuits and parasitic capacitance.

Epitaxial shells around vertical core channels boost carrier mobility while enabling denser CMOS and CFET transistor stacking beyond 2D scaling.

A metal gate extended into trenches below isolation improves bottom-channel control in nanosheet FETs and cuts leakage.

A dual-layer inner spacer uses an etch-resistant outer layer and low-k inner layer to protect source/drain regions while cutting parasitic capacitance.

Independent GAAFET nanowire breaking enables one OTPROM cell to store multiple bits, improving logic programming and data confidentiality.

A protruding lower field insulating film between fin patterns improves current control and suppresses short channel effects in scaled multi-gate transistors.

Etch-stop and blocking layers isolate CFET vertical contacts from the silicon substrate, preventing over-etch shorts and preserving gap margin.

A recessed source/drain filled with a metal-semiconductor layer improves silicide formation in scaled contacts and lowers resistance.

Gate voltage raises domain boundary density in a multiferroic antiferromagnetic channel to control magnon spin transport without large magnetic fields.

A Ge-diffusion and etch sequence recesses STI near the bottom channel so the gate contacts fin sidewalls, reducing leakage and capacitance.

A mixed GAA SRAM cell combines nanosheet and nanowire transistors with wider bit lines to raise speed, cut leakage, and avoid write assist circuitry.

Dog-bone channel shaping and wider inner spacers preserve junction overlap in multi-gate transistors, cutting junction resistance by 25% to 35%.

Nitrogen-rich TiN deposited by PEALD wraps GAA nanosheets to strengthen gate control, cut short-channel effects, and lower threshold voltage.

Nested through-channel and gate-all-around gates enable multi-threshold MOSFETs while limiting leakage, parasitic capacitance, and scaling complexity.

Using S-polarized resist removal before P-polarized or unpolarized annealing improves dopant activation while limiting thermal damage.

A single gate combines tunneling and 2D electron gas formation to keep sub-60 mV/dec switching while raising TFET current.

Different GAA SRAM cells on one chip use distinct threshold voltages and work functions to balance speed, power, and shared cell size.

A Si/SiGe quantum-well spacer structure improves carrier tunneling, lowers program/erase voltage, and preserves memory window over cycling.

ALD tunes gate dielectric thickness across wide and narrow trenches to boost short-channel speed while limiting leakage and high-voltage risk.

A T-shaped stacked nanosheet structure adds conductive area through recessed semiconductor layers to raise drive current in scaled transistors.

A merged gate barrier layer blocks metal migration and keeps work function metal thickness uniform in stacked semiconductor channels.

A bottom dielectric constrains backside power rail vias in GAA devices to boost rail density, cut resistance, and avoid gate or source-drain shorts.

Narrowed center dielectric fins improve metal gate fill around GAA nanowires, cutting resistance and short risk at tighter spacing.

Simultaneous spacer formation on dummy gates and channel grooves improves alignment consistency and reduces process variation in lateral GAA-FET fabrication.

A 2D interlayer and high-electron-affinity surface treatment suppress work function pinning and lower Schottky barrier contact resistivity.

A sacrificial plug protects bottom nanoribbon gates during selective etching, enabling dual workfunction metals with tighter ribbon spacing.

Stacked silicon and non-semiconductor monolayers boost carrier mobility while blocking dopant diffusion and reducing defects in semiconductor layers.

Directional O2 plasma forms tungsten oxide on protected regions, allowing wet etching to clear sidewalls while retaining contact tungsten.

Silicide and silicon separation layers plus bottom dielectric isolation cut contact resistance and parasitic capacitance in stacked nanosheet ICs.

Surface curvature and passivation layers reduce stress and atomic migration at FinFET source/drain epitaxial interfaces.

Chlorine-assisted SiGe:B epitaxy drives hGAA source/drain growth onto <100> surfaces, reducing faceting, poor wetting, and voids.

A TiSiN barrier blocks aluminum diffusion in a gate-all-around gate stack, enabling threshold voltage tuning and short-channel control.