FinFET Isolation Structure for Short-Channel Current Control
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Solution Overview
Problem
Current semiconductor devices face challenges in scaling down multi-gate transistors and effectively controlling current without increasing gate length, while also suppressing short channel effects.
Innovation Solution
The semiconductor device design includes fin-type patterns with epitaxial patterns and insulating films, where a lower field insulating film with protrusions and epitaxial etch stop films are used to enhance control and reliability, and source/drain contacts are strategically positioned to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistor gate length is increased to improve current control capability, then current control capability is improved, but device area increases
Solution Approach 1:
The patent transitions from planar 2D channel to three-dimensional multi-gate structures (FinFET, nanowire, multi-channel active patterns). By adding vertical dimension and creating multi-gate configurations, the effective channel width is increased without proportionally increasing the planar footprint, thereby improving current control capability while maintaining compact device area.
2Productivity
If multi-gate transistor is scaled down to increase integration density, then integration density is improved, but short channel effect suppression becomes more difficult
Solution Approach 1:
The patent employs three-dimensional multi-gate structures including FinFET and nanowire configurations. These structures provide enhanced gate control over the channel from multiple directions (top, bottom, and sidewalls), which effectively suppresses short channel effects even when the transistor dimensions are scaled down to increase integration density.
3Reliability
If field insulating film is made thicker to improve electrical isolation, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the field insulating film into multiple distinct layers: lower field insulating film and upper field insulating film, with etch stop films positioned between them and other structures. This segmentation allows each layer to be optimized for specific functions (isolation, etch protection, planarization) and simplifies the manufacturing process by enabling selective etching and deposition operations on individual layers.
4Manufacturing precision
If epitaxial pattern sidewalls are protected with multiple etch stop films to improve manufacturing precision, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a segmented protection system with lower epitaxial etch stop film and upper epitaxial etch stop film positioned at different vertical levels. This segmentation enables selective etching operations to access different sidewall regions without affecting other structures, thereby improving manufacturing precision while managing complexity through functional specialization of each film layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for improved reliability and performance by effectively controlling current and suppressing short channel effects, enabling better scalability and reduced short channel effects in multi-gate transistors.
Implementation Method 1
a lower field insulating film disposed on the substrate so as to extend on (e.g., cover) a sidewall of the first fin-type pattern and a sidewall of the second fin-type pattern, wherein the lower field insulating film includes a protrusion protruding in a third direction
Implementation Method 2
a first epitaxial pattern disposed on and connected to the first fin-type pattern, a second epitaxial pattern disposed on and connected to the second fin-type pattern
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a first fin-type pattern and a second fin-type pattern on a substrate, a first epitaxial pattern on the first fin-type pattern, a second epitaxial pattern on the second fin-type pattern, and a lower field insulating film on the substrate and extends on a sidewall of the first fin-type pattern and a sidewall of the second fin-type pattern, wherein the lower field insulating film includes a protrusion protruding in a third direction. The protrusion of the lower field insulating film may be between the first fin-type pattern and the second fin-type pattern, and a vertical level of a top surface of the protrusion of the lower field insulating film increases and then decreases with increasing distance from the sidewall of the first fin-type pattern.